Try the following modifications, please note that you need to compile uboot first and then compile all the android code
xiong@server:/users/xiong/work/amlogic/vim1s/bootloader/uboot$ git diff
diff --git a/arch/arm/mach-meson/s4/hdmitx_clk.c b/arch/arm/mach-meson/s4/hdmitx_clk.c
index 6e474c1595..d3f1f14a65 100644
--- a/arch/arm/mach-meson/s4/hdmitx_clk.c
+++ b/arch/arm/mach-meson/s4/hdmitx_clk.c
@@ -341,7 +341,7 @@ void set_hpll_clk_out(unsigned int clk)
WAIT_FOR_PLL_LOCKED(P_ANACTRL_HDMIPLL_CTRL0);
pr_info("HPLL: 0x%x\n", hd_read_reg(P_ANACTRL_HDMIPLL_CTRL0));
break;
- case 292300:
+ case 297600:
hd_write_reg(P_ANACTRL_HDMIPLL_CTRL0, 0x3b0004C2);//800x480
if (frac_rate)
hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x0001cccc);
@@ -826,7 +826,7 @@ static struct hw_enc_clk_val_group setting_enc_clk_val_24[] = {
1, VIU_ENCP, 251750, 4, 4, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
{{HDMIV_800x480p60hz,
GROUP_END},
- 1, VIU_ENCP, 292300, 4, 4, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ 1, VIU_ENCP, 297600, 4, 4, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
{{HDMIV_800x600p60hz,
GROUP_END},
1, VIU_ENCP, 400000, 4, 2, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
diff --git a/arch/arm/mach-meson/sc2/hdmitx_clk.c b/arch/arm/mach-meson/sc2/hdmitx_clk.c
index 85ac9e9007..ab5a1934cd 100644
--- a/arch/arm/mach-meson/sc2/hdmitx_clk.c
+++ b/arch/arm/mach-meson/sc2/hdmitx_clk.c
@@ -353,7 +353,7 @@ void set_hpll_clk_out(unsigned int clk)
WAIT_FOR_PLL_LOCKED(P_ANACTRL_HDMIPLL_CTRL0);
pr_info("HPLL: 0x%x\n", hd_read_reg(P_ANACTRL_HDMIPLL_CTRL0));
break;
- case 292300:
+ case 297600:
hd_write_reg(P_ANACTRL_HDMIPLL_CTRL0, 0x3b0004C2);//800x480
if (frac_rate)
hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x0001cccc);
@@ -836,7 +836,7 @@ static struct hw_enc_clk_val_group setting_enc_clk_val_24[] = {
1, VIU_ENCP, 251750, 4, 4, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
{{HDMIV_800x480p60hz,
GROUP_END},
- 1, VIU_ENCP, 292300, 4, 4, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ 1, VIU_ENCP, 297600, 4, 4, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
{{HDMIV_800x600p60hz,
GROUP_END},
1, VIU_ENCP, 400000, 4, 2, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
xiong@server:/users/xiong/work/amlogic/vim1s/common$ git diff
diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_common/hdmi_parameters.c b/drivers/amlogic/media/vout/hdmitx/hdmi_common/hdmi_parameters.c
index a57ccca41816..161bdf76a10f 100644
--- a/drivers/amlogic/media/vout/hdmitx/hdmi_common/hdmi_parameters.c
+++ b/drivers/amlogic/media/vout/hdmitx/hdmi_common/hdmi_parameters.c
@@ -1823,9 +1823,9 @@ static struct hdmi_format_para fmt_para_vesa_800x480p60_4x3 = {
.progress_mode = 1,
.scrambler_en = 0,
.tmds_clk_div40 = 0,
- .tmds_clk = 29230,
+ .tmds_clk = 29760,
.timing = {
- .pixel_freq = 29230,
+ .pixel_freq = 29760,
.h_freq = 30000,
.v_freq = 60000,
.vsync = 60,
diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c
index b1710822ebb7..c49576ce25e9 100644
--- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c
+++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c
@@ -681,7 +681,7 @@ static struct hw_enc_clk_val_group setting_enc_clk_val_24[] = {
251750, 4, 4, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
{{HDMIV_800x480p60hz,
HDMI_VIC_END},
- 292300, 4, 4, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ 297600, 4, 4, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
{{HDMIV_800x600p60hz,
HDMI_VIC_END},
400000, 4, 2, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_g12a.c b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_g12a.c
index 1df4a29c5fda..c1be325f69d7 100644
--- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_g12a.c
+++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_g12a.c
@@ -419,7 +419,7 @@ void set_g12a_hpll_clk_out(unsigned int frac_rate, unsigned int clk)
WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
printk("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
break;
- case 292300:
+ case 297600:
hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b0004C2);//800x480
if (frac_rate)
hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x0001cccc);