Mainline u-boot for khadas sbc

Announcements
21

Hi @hyphop

I wanted to try Mainline uboot for vim2 and I see 2 different files

[ ] VIM2.u-boot.sd.bin 2020-05-22 04:31 1.0M
[ ] VIM2.u-boot.spi.bin 2020-05-22 04:31 1.0M
[ ] VIM2.uboot-mainline.emmc.aml.img

Why can’t we just have a single uboot image for emmc and sd? This is the normal case for AW & RK uboots, IDK why aml have to make it so complicated.
the emmc-aml is to be used with burning tool so can I just use sd.bin for sd and also emmc ?

Currently I will try to use the sd.bin for testing purpose, will get back to you with more updates and questions.

Thanks.

22

why stil want to use the usb burning tool when dd does the job nicely ?

23

why nobody read README, plz read at first it https://dl.khadas.com/Firmware/uboot/main-line/README.txt

2 Likes
24

in some situation we can use only usb-burn-tool (for example looped broken uboot ) and it must be

25

I am reading it now, IDK why you named the file sd though.

I am trying this on vim2 but it is not booting.

I have Android on emmc and Flashed mainline-uboot to sd card and used extlinux.

Am I missing anything else?

26

sd uboot start only with clear emmc / or mask rom mode (tst mode etc… and only for VIM1 VIM2 Edge)

27

Oh Ok.
I will try maskrom mode now.

Thank you for the quick response. Also If I flash the same image on emmc then there is not need for maskrom right ? Just asking to make it clear.

UPDATE: With maskrom mode it works :smiley:

UPDATE2: Looks like I have to enter maskrom mode everytime I want to boot from sd card???, To solve this maybe Khadas should come up with a better uboot from android.

Thank You again.

28

its hardware boot seq !
write this uboot to emmc and forget about android
i still dont undestand why you need android on emmc if u run linux
this uboot (writed to emmc ) can start your system from any sources USB / SD / EMMC / PXE / UEFI
and no need stupid multiboot activation - its already works

1 Like
29

I know dear, I am not looking for a solution for myself, I always had Linux on EMMC, I am a maintainer and I need to think from normal users point of view and try to make things as easy as possible for the users to get Manjaro linux.

I am always testing in multiple ways to find the best solution for non technical users.

It is all because of the vendor uboot on emmc. But there will always be a conflict between vendor uboot and mainline uboot for all arm devices.

Thanks.

30

i think linux distro mainteners should educate their target linux user to rip android and any android related quirk from the boards they play with.
linux is self sufficient, vims are not tv boxes, they are prototyping boards, they do not need android. the buyers wanting to kep android in their emmc are not serious linux users. using stable linux from a sd card when emmc direct installation is available look like non serious enough user, they do not deserve any specuial treatment like dual boot or special uboot imho.

1 Like
31

no need to think what user is noob ( you need to instill good taste in people - and improve them ) and no need to give strange advice like this : plz install android if u need run linux :wink:

It is all because of the vendor uboot on emmc. But there will always be a conflict between vendor uboot and mainline uboot for all arm devices.

i dont have any conflicts (just write whole system with all required to emmc ) :wink:

1 Like
32

what is really this “vendor uboot” or “vendor firmware” thing ?
if vendor means Khadas, then listen to hyphop who represents Khadas.
If vendor is Amlogic wanting you to use their weird android shit, then screw this vendor and listen to the board manufacturer.

1 Like
33

This was only because before mainline uboot was not so stable. Now that you have got mainline uboot stable then we can prepare a mainline uboot images and ask users to get rid of android.

Maybe you never tried random options, we get asked random questions on multi boot options like have 1 os on emmc and run another one from sd or usb.
This cause conflicts if different uboots are used this is from my experience of other boards and other linux os’s.
I understand that we cannot give users all solutions to their questions but atleast we can streamline it for users.

Also diy boards are mostly purchased by hobbiest to play around with and the whole point of buying diy boards is to try almost all possible operating systems.

This is not conflict of interest or argument, this is just a discussion on how we can improve the booting methods to get more users to use amlogic soc.

If you see Edge series we already have mainline uboot and the same uboot is used on sd and emmc and there is very less conflict between vendor uboot and mainline uboot as the hardware boot sequence is very straight forward which is not the case for amlogic.
I also have allwinner devices which we maintain, vendor uboot is present on emmc with android and still we can boot directly into sd card with mainline uboot without having to enter any maskrom. Mode.

I am trying to compare amlogic boot sequence with other oems as they have a very simple way of booting which is very helpful for users. Amlogic methods can irritate the users and end with disappointment.

I hope you get a clear picture of my way of doing things for what I maintain.

Relax man, this is just a discussion to improve software support for khadas devices and not a fight to get things working in my ways. Hahaha
Cheers.

2 Likes
34

@ravelo I agree with you on this point, Khadas has done way more work in this field than Amlogic,
I wish Khadas just bought the Amlogic company :crazy_face: and there would be no problem at all related to Vendor uBoot and Vendor Firmware, atleast then no one needs to get complained about

2 Likes
35

I would like to celebrate the constant work of the khadas team and of all the developers helping them.
Now that we finally have working and stable uboot and mainline linux kernel, hooray, well done, kudos, and relax !
We can sincerly begin to forget the bad old days (of android in the emmc as the starting point for everything else) and the weird actions needed back then (boot to SD , use some script to rewrite emmc).

I hope all this will help Manjaro (and Arch based distro ) manage to attract more users, especially on the khadas boards we choose to follow (since the very beginning, for a few of us).

3 Likes
36

Thanks you hyphop!!

I have flashed mainline u-boot in the SPI and now I can boot GNU/Linux from the SD and Android from EMMC. Also the green screen problem and the USB keyboard/mouse disabled have gone.

37

YES its good solution ! just change kbi bootmode from SPI to EMMC and back (mainline uboot start sd / usb and vendor uboot start mmc )

PS: another questions why u still need android :wink: ?

38

Hello @hyphop

I am back with some debugging and booting issues hahaha.
VIm1 works fine no issues at all even with android on emmc.
Vim2 works too but need to enter multiboot mode for every boot.
Vim3 gets stuck in uboot.env not found error.

This post is for vim3.

  1. I erase my emmc using store init 3 as explained on Khadas Docs
  2. Created Manjaro OS image with Mainline uboot. Mainline uboot = VIM3.u-boot.sd.bin from khadas download page.
  3. Tried to boot from sd card with Manjaro OS mainline uboot flashed on sd card.

Here is the uart output for clear information.

                                                                                       
G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:0;READ:0;CHK:1F;READ:0;CHK:
1F;READ:0;CHK:1F;SD?:0;SD:0;READ:0;0.                                                  
bl2_stage_init 0x01                                                                    
bl2_stage_init 0x81                                                                    
hw id: 0x0000 - pwm id 0x01                                                            
bl2_stage_init 0xc1                                                                    
bl2_stage_init 0x02                                                                    
                                                                                       
no sdio debug board detected                                                           
L0:00000000                                                                            
L1:20000703                                                                            
L2:00008067                                                                            
L3:14000000                                                                            
B2:00402000                                                                            
B1:e0f83180                                                                            
                                                                                       
TE: 451538                                                                             
                                                                                       
BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz                
                                                                                       
Board ID = 8                                                                           
Set A53 clk to 24M                                                                     
Set A73 clk to 24M                                                                     
Set clk81 to 24M                                                                       
A53 clk: 1200 MHz                                                                      
A73 clk: 1200 MHz                                                                      
CLK81: 166.6M                                                                          
smccc: 00072bb0                                                                        
DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01                
board id: 8                                                                            
Load FIP HDR from SD, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0      
fw parse done                                                                          
Load ddrfw from SD, src: 0x00060200, des: 0xfffd0000, size: 0x0000c000, part: 0        
Load ddrfw from SD, src: 0x00038200, des: 0xfffd0000, size: 0x00004000, part: 0        
PIEI prepare done                                                                      
fastboot data load                                                                     
fastboot data verify                                                                   
verify result: 266                                                                     
Cfg max: 4, cur: 1. Board id: 255. Force loop cfg                                      
LPDDR4 probe                                                                           
ddr clk to 1608MHz                                                                     
Load ddrfw from SD, src: 0x0003c200, des: 0xfffd0000, size: 0x0000c000, part: 0        
                                                                                       
dmc_version 0001                                                                       
Check phy result                                                                       
INFO : End of CA training                                                              
INFO : End of initialization                                                           
INFO : Training has run successfully!                                                  
Check phy result                                                                       
INFO : End of initialization                                                           
INFO : End of read enable training                                                     
INFO : End of fine write leveling                                                      
INFO : End of Write leveling coarse delay                                              
INFO : Training has run successfully!                                                  
Check phy result                                                                       
INFO : End of initialization                                                           
INFO : End of read dq deskew training                                                  
INFO : End of MPR read delay center optimization                                       
INFO : End of write delay center optimization                                          
INFO : End of read delay center optimization                                           
INFO : End of max read latency training                                                
INFO : Training has run successfully!                                                  
1D training succeed                                                                    
Load ddrfw from SD, src: 0x00048200, des: 0xfffd0000, size: 0x0000c000, part: 0        
Check phy result                                                                       
INFO : End of initialization                                                           
INFO : End of 2D read delay Voltage center optimization                                
INFO : End of 2D read delay Voltage center optimization                                
INFO : End of 2D write delay Voltage center optimization                               
INFO : End of 2D write delay Voltage center optimization                               
INFO : Training has run successfully!                                                  
                                                                                       
channel==0                                                                             
RxClkDly_Margin_A0==97 ps 10                                                           
TxDqDly_Margin_A0==106 ps 11                                                           
RxClkDly_Margin_A1==58 ps 6                                                            
TxDqDly_Margin_A1==106 ps 11                                                           
TrainedVREFDQ_A0==27                                                                   
TrainedVREFDQ_A1==27                                                                   
VrefDac_Margin_A0==28                                                                  
DeviceVref_Margin_A0==26                                                               
VrefDac_Margin_A1==30                                                                  
DeviceVref_Margin_A1==27                                                               
                                                                                       
                                                                                       
channel==1                                                                             
RxClkDly_Margin_A0==97 ps 10                                                           
TxDqDly_Margin_A0==106 ps 11                                                           
RxClkDly_Margin_A1==97 ps 10                                                           
TxDqDly_Margin_A1==106 ps 11                                                           
TrainedVREFDQ_A0==26                                                                   
TrainedVREFDQ_A1==26                                                                   
VrefDac_Margin_A0==28                                                                  
DeviceVref_Margin_A0==25                                                               
VrefDac_Margin_A1==26                                                                  
DeviceVref_Margin_A1==25                                                               
                                                                                       
 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004                                 
                                                                                       
soc_vref_reg_value 0x 00000027 00000027 00000026 00000025 00000027 00000025 00000025 00
000025 00000025 00000026 00000027 00000026 00000025 00000026 00000025 00000025 00000025
 00000025 00000025 00000025 00000023 00000026 00000026 00000025 00000025 00000025 00000
027 00000027 00000025 00000024 00000027 00000027 dram_vref_reg_value 0x 00000013       
2D training succeed                                                                    
aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19                
auto size-- 65535DDR cs0 size: 2048MB                                                  
DDR cs1 size: 2048MB                                                                   
DMC_DDR_CTRL: 00e00024DDR size: 3928MB                                                 
cs0 DataBus test pass                                                                  
cs1 DataBus test pass                                                                  
cs0 AddrBus test pass                                                                  
cs1 AddrBus test pass                                                                  
                                                                                       
100bdlr_step_size ps== 450                                                             
result report                                                                          
boot times 0Enable ddr reg access                                                      
Load FIP HDR from SD, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0      
Load BL3X from SD, src: 0x00078200, des: 0x01768000, size: 0x000a0000, part: 0         
0.0;M3 CHK:0;cm4_sp_mode 0                                                             
MVN_1=0x00000000                                                                       
MVN_2=0x00000000                                                                       
[Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]               
OPS=0x10                                                                               
ring efuse init                                                                        
chipver efuse init                                                                     
29 0b 10 00 01 1d 0a 00 00 03 35 38 47 47 52 50                                        
[0.018961 Inits done]                                                                  
secure task start!                                                                     
high task start!                                                                       
low task start!                                                                        
run into bl31                                                                          
NOTICE:  BL31: v1.3(release):4fc40b1                                                   
NOTICE:  BL31: Built : 15:58:17, May 22 2019                                           
NOTICE:  BL31: G12A normal boot!                                                       
NOTICE:  BL31: BL33 decompress pass                                                    
ERROR:   Error initializing runtime service opteed_fast                                
                                                                                       
                                                                                       
U-Boot 2020.04 (Jul 16 2020 - 16:51:18 +0900) khadas-vim3                              
                                                                                       
Model: Khadas VIM3                                                                     
SoC:   Amlogic Meson G12B (A311D) Revision 29:b (10:2)                                 
DRAM:  3.8 GiB                                                                         
MMC:   sd@ffe03000: 0, sd@ffe05000: 1, mmc@ffe07000: 2                                 
Loading Environment from FAT... detect... booted from sd...                            
"uboot.env" not found on mmc-1:1... OK

I cannot enter in uboot cli to check env it is using

Please advice what I am missing here.

Thanks.

UPDATE:
I tried krescue image and it is the same.

G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:0;READ:0;CHK:1F;G12B:BL:6e7
c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:0;READ:0;CHK:1F;READ:0;CHK:1F;READ:0;C
HK:1F;SD?:0;SD:0;READ:0;0.                                                             
bl2_stage_init 0x01                                                                    
bl2_stage_init 0x81                                                                    
hw id: 0x0000 - pwm id 0x01                                                            
bl2_stage_init 0xc1                                                                    
bl2_stage_init 0x02                                                                    
                                                                                       
no sdio debug board detected                                                           
L0:00000000                                                                            
L1:20000703                                                                            
L2:00008067                                                                            
L3:14000000                                                                            
B2:00402000                                                                            
B1:e0f83180                                                                            
                                                                                       
TE: 496423                                                                             
                                                                                       
BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz                
                                                                                       
Board ID = 8                                                                           
Set A53 clk to 24M                                                                     
Set A73 clk to 24M                                                                     
Set clk81 to 24M                                                                       
A53 clk: 1200 MHz                                                                      
A73 clk: 1200 MHz                                                                      
CLK81: 166.6M                                                                          
smccc: 0007db05                                                                        
DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01                
board id: 8                                                                            
Load FIP HDR from SD, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0      
fw parse done                                                                          
Load ddrfw from SD, src: 0x00060200, des: 0xfffd0000, size: 0x0000c000, part: 0        
Load ddrfw from SD, src: 0x00038200, des: 0xfffd0000, size: 0x00004000, part: 0        
PIEI prepare done                                                                      
fastboot data load                                                                     
fastboot data verify                                                                   
verify result: 266                                                                     
Cfg max: 4, cur: 1. Board id: 255. Force loop cfg                                      
LPDDR4 probe                                                                           
ddr clk to 1608MHz                                                                     
Load ddrfw from SD, src: 0x0003c200, des: 0xfffd0000, size: 0x0000c000, part: 0        
                                                                                       
dmc_version 0001                                                                       
Check phy result                                                                       
INFO : End of CA training                                                              
INFO : End of initialization                                                           
INFO : Training has run successfully!                                                  
Check phy result                                                                       
INFO : End of initialization                                                           
INFO : End of read enable training                                                     
INFO : End of fine write leveling                                                      
INFO : End of Write leveling coarse delay                                              
INFO : Training has run successfully!                                                  
Check phy result                                                                       
INFO : End of initialization                                                           
INFO : End of read dq deskew training                                                  
INFO : End of MPR read delay center optimization                                       
INFO : End of write delay center optimization                                          
INFO : End of read delay center optimization                                           
INFO : End of max read latency training                                                
INFO : Training has run successfully!                                                  
1D training succeed                                                                    
Load ddrfw from SD, src: 0x00048200, des: 0xfffd0000, size: 0x0000c000, part: 0        
Check phy result                                                                       
INFO : End of initialization                                                           
INFO : End of 2D read delay Voltage center optimization                                
INFO : End of 2D read delay Voltage center optimization                                
INFO : End of 2D write delay Voltage center optimization                               
INFO : End of 2D write delay Voltage center optimization                               
INFO : Training has run successfully!                                                  
                                                                                       
channel==0                                                                             
RxClkDly_Margin_A0==87 ps 9                                                            
TxDqDly_Margin_A0==106 ps 11                                                           
RxClkDly_Margin_A1==77 ps 8                                                            
TxDqDly_Margin_A1==97 ps 10                                                            
TrainedVREFDQ_A0==26                                                                   
TrainedVREFDQ_A1==27                                                                   
VrefDac_Margin_A0==29                                                                  
DeviceVref_Margin_A0==26                                                               
VrefDac_Margin_A1==29                                                                  
DeviceVref_Margin_A1==27                                                               
                                                                                       
                                                                                       
channel==1                                                                             
RxClkDly_Margin_A0==106 ps 11                                                          
TxDqDly_Margin_A0==106 ps 11                                                           
RxClkDly_Margin_A1==97 ps 10                                                           
TxDqDly_Margin_A1==106 ps 11                                                           
TrainedVREFDQ_A0==26                                                                   
TrainedVREFDQ_A1==26                                                                   
VrefDac_Margin_A0==28                                                                  
DeviceVref_Margin_A0==25                                                               
VrefDac_Margin_A1==27                                                                  
DeviceVref_Margin_A1==25                                                               
                                                                                       
 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004                                 
                                                                                       
soc_vref_reg_value 0x 00000028 00000027 00000026 00000025 00000027 00000025 00000025 00
000025 00000025 00000026 00000027 00000026 00000025 00000026 00000025 00000025 00000025
 00000025 00000025 00000025 00000023 00000026 00000026 00000025 00000025 00000025 00000
027 00000027 00000025 00000024 00000027 00000027 dram_vref_reg_value 0x 00000013       
2D training succeed                                                                    
aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19                
auto size-- 65535DDR cs0 size: 2048MB                                                  
DDR cs1 size: 2048MB                                                                   
DMC_DDR_CTRL: 00e00024DDR size: 3928MB                                                 
cs0 DataBus test pass                                                                  
cs1 DataBus test pass                                                                  
cs0 AddrBus test pass                                                                  
cs1 AddrBus test pass                                                                  
                                                                                       
100bdlr_step_size ps== 450                                                             
result report                                                                          
boot times 0Enable ddr reg access                                                      
Load FIP HDR from SD, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0      
Load BL3X from SD, src: 0x00078200, des: 0x01768000, size: 0x000a0000, part: 0         
0.0;M3 CHK:0;cm4_sp_mode 0                                                             
MVN_1=0x00000000                                                                       
MVN_2=0x00000000                                                                       
[Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]               
OPS=0x10                                                                               
ring efuse init                                                                        
chipver efuse init                                                                     
29 0b 10 00 01 1d 0a 00 00 03 35 38 47 47 52 50                                        
[0.018960 Inits done]                                                                  
secure task start!                                                                     
high task start!                                                                       
low task start!                                                                        
run into bl31                                                                          
NOTICE:  BL31: v1.3(release):4fc40b1                                                   
NOTICE:  BL31: Built : 15:58:17, May 22 2019                                           
NOTICE:  BL31: G12A normal boot!                                                       
NOTICE:  BL31: BL33 decompress pass                                                    
ERROR:   Error initializing runtime service opteed_fast                                
                                                                                       
                                                                                       
U-Boot 2020.04 (Jul 03 2020 - 16:33:07 +0900) khadas-vim3                              
                                                                                       
Model: Khadas VIM3                                                                     
SoC:   Amlogic Meson G12B (A311D) Revision 29:b (10:2)                                 
DRAM:  3.8 GiB                                                                         
MMC:   sd@ffe03000: 0, sd@ffe05000: 1, mmc@ffe07000: 2                                 
Loading Environment from FAT... detect... booted from sd...                            
"uboot.env" not found on mmc-1:1... OK

Please advice.

Thanks.

39

its not error it just warning - and told about 1st fat partition not found (uboot env saved in restored to
uboot.env on 1st fat partition ) but its not must be a problem - if uboot.env cant loaded booting must continue ayway

anyway if you booting was freezed in uboot stage - i must reproduce your situation and try understand what a problem!!!

Vim2 works too but need to enter multiboot mode for every boot.

didnt undestand - what is multiboot mode ? ;)))

I tried krescue image and it is the same.

yes its must be same as dl.khadas.com - Index of /firmware/uboot/mainline/

PS: last uboot images - can goto cli mode (by SPACE or CRTL+C - not by ANY key as was before )

PSS: try to undestand whats wrong !!! its just for checking

  1. write last openwrt image to VIM3 via krescue to emmc - CHECK how its works
  2. write only uboot mainline via same krescue - write openwrt sd image to sd or usb dl.khadas.com - Index of /firmware/openwrt/ - CHECK how its works
  3. clear emmc and start openwrt from sd - - CHECK how its works

for me all steps was works fine - and its same mainline uboot

PSSSS: write me about your results - goodluck

40

Leave this for now :wink:

I tried krescue and it is stuck on same place uboot.env not found but when I try to boot from sd card with Libreelec using Mainline uboot it boot pass this error.

Yes ofcourse I tried SPACE but it doesn’t even reach the uboot cli position for it to enter into uboot cli :frowning:

Only If I can get krescue to boot, as I said krescue also get stuck at the same stage with uboot.env not found.