Mainline u-boot for khadas sbc

try another way https://dl.khadas.com/Firmware/uboot/mainline/VIM3L.uboot-mainline.emmc.aml.img
write via aml-burn-tool - may be it can help

without sd cards and any usb - uboot still freezed ?

My emmc is blank as I erased it completely,
Flashed krescue in sdcard
Insert sd card in Vim3
Stuck at uboot.env not found.

OK! write sd openwrt image dl.khadas.com - Index of /firmware/openwrt/ - i have test it many times and its works for me (any combinations)
WRITE ME BACK YOUR RESULTS

did u try other SD card ?

PS: try without usb keyboard !!!

Sure.
I only have usb-c power and sd card with the vim3 openwrt image.
Log below.

Press CTRL-A Z for help on special keys

G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:0;READ:0;CHK:1F;READ:0;CHK.
bl2_stage_init 0x01
bl2_stage_init 0x81
hw id: 0x0000 - pwm id 0x01
bl2_stage_init 0xc1
bl2_stage_init 0x02

no sdio debug board detected 
L0:00000000
L1:20000703
L2:00008067
L3:14000000
B2:00402000
B1:e0f83180                                                                            
                                                                                       
TE: 311970                                                                             
                                                                                       
BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz                
                                                                                       
Board ID = 8                                                                           
Set A53 clk to 24M                                                                     
Set A73 clk to 24M                                                                     
Set clk81 to 24M                                                                       
A53 clk: 1200 MHz                                                                      
A73 clk: 1200 MHz                                                                      
CLK81: 166.6M                                                                          
smccc: 00050a80                                                                        
DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01                
board id: 8                                                                            
Load FIP HDR from SD, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0      
fw parse done                                                                          
Load ddrfw from SD, src: 0x00060200, des: 0xfffd0000, size: 0x0000c000, part: 0        
Load ddrfw from SD, src: 0x00038200, des: 0xfffd0000, size: 0x00004000, part: 0        
PIEI prepare done                                                                      
fastboot data load                                                                     
fastboot data verify                                                                   
verify result: 266                                                                     
Cfg max: 4, cur: 1. Board id: 255. Force loop cfg                                      
LPDDR4 probe                                                                           
ddr clk to 1608MHz                                                                     
Load ddrfw from SD, src: 0x0003c200, des: 0xfffd0000, size: 0x0000c000, part: 0        
                                                                                       
dmc_version 0001                                                                       
Check phy result                                                                       
INFO : End of CA training                                                              
INFO : End of initialization                                                           
INFO : Training has run successfully!                                                  
Check phy result                                                                       
INFO : End of initialization                                                           
INFO : End of read enable training                                                     
INFO : End of fine write leveling                                                      
INFO : End of Write leveling coarse delay                                              
INFO : Training has run successfully!                                                  
Check phy result                                                                       
INFO : End of initialization                                                           
INFO : End of read dq deskew training                                                  
INFO : End of MPR read delay center optimization                                       
INFO : End of write delay center optimization                                          
INFO : End of read delay center optimization                                           
INFO : End of max read latency training                                                
INFO : Training has run successfully!                                                  
1D training succeed                                                                    
Load ddrfw from SD, src: 0x00048200, des: 0xfffd0000, size: 0x0000c000, part: 0        
Check phy result                                                                       
INFO : End of initialization                                                           
INFO : End of 2D read delay Voltage center optimization                                
INFO : End of 2D read delay Voltage center optimization                                
INFO : End of 2D write delay Voltage center optimization                               
INFO : End of 2D write delay Voltage center optimization                               
INFO : Training has run successfully!                                                  
                                                                                       
channel==0                                                                             
RxClkDly_Margin_A0==87 ps 9                                                            
TxDqDly_Margin_A0==106 ps 11                                                           
RxClkDly_Margin_A1==77 ps 8                                                            
TxDqDly_Margin_A1==106 ps 11                                                           
TrainedVREFDQ_A0==26                                                                   
TrainedVREFDQ_A1==27                                                                   
VrefDac_Margin_A0==29                                                                  
DeviceVref_Margin_A0==26                                                               
VrefDac_Margin_A1==30                                                                  
DeviceVref_Margin_A1==27                                                               
                                                                                       
                                                                                       
channel==1                                                                             
RxClkDly_Margin_A0==97 ps 10                                                           
TxDqDly_Margin_A0==106 ps 11                                                           
RxClkDly_Margin_A1==97 ps 10                                                           
TxDqDly_Margin_A1==106 ps 11                                                           
TrainedVREFDQ_A0==26                                                                   
TrainedVREFDQ_A1==26                                                                   
VrefDac_Margin_A0==27                                                                  
DeviceVref_Margin_A0==25                                                               
VrefDac_Margin_A1==27                                                                  
DeviceVref_Margin_A1==25                                                               
                                                                                       
 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004                                 
                                                                                       
soc_vref_reg_value 0x 00000027 00000027 00000026 00000025 00000027 00000025 00000026 03
2D training succeed                                                                    
aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19                
auto size-- 65535DDR cs0 size: 2048MB                                                  
DDR cs1 size: 2048MB                                                                   
DMC_DDR_CTRL: 00e00024DDR size: 3928MB                                                 
cs0 DataBus test pass                                                                  
cs1 DataBus test pass                                                                  
cs0 AddrBus test pass                                                                  
cs1 AddrBus test pass                                                                  
                                                                                       
100bdlr_step_size ps== 450                                                             
result report                                                                          
boot times 0Enable ddr reg access                                                      
Load FIP HDR from SD, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0      
Load BL3X from SD, src: 0x00078200, des: 0x01768000, size: 0x000a0000, part: 0         
0.0;M3 CHK:0;cm4_sp_mode 0                                                             
MVN_1=0x00000000                                                                       
MVN_2=0x00000000                                                                       
[Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]               
OPS=0x10                                                                               
ring efuse init                                                                        
chipver efuse init                                                                     
29 0b 10 00 01 1d 0a 00 00 03 35 38 47 47 52 50                                        
[0.018961 Inits done]                                                                  
secure task start!                                                                     
high task start!                                                                       
low task start!                                                                        
run into bl31                                                                          
NOTICE:  BL31: v1.3(release):4fc40b1                                                   
NOTICE:  BL31: Built : 15:58:17, May 22 2019                                           
NOTICE:  BL31: G12A normal boot!                                                       
NOTICE:  BL31: BL33 decompress pass                                                    
ERROR:   Error initializing runtime service opteed_fast                                
                                                                                       
                                                                                       
U-Boot 2020.04 (Jun 23 2020 - 13:58:11 +0900) khadas-vim3                              
                                                                                       
Model: Khadas VIM3                                                                     
SoC:   Amlogic Meson G12B (A311D) Revision 29:b (10:2)                                 
DRAM:  3.8 GiB                                                                         
MMC:   sd@ffe03000: 0, sd@ffe05000: 1, mmc@ffe07000: 2                                 
Loading Environment from FAT... detect... booted from sd...                            
"uboot.env" not found on mmc-1:1... OK  

It is just stuck here :frowning:

check just now - forks fine

WORKS FINE

additional video

PS: VIM3 ver12 - was tested

PSS: plz check other SD cards - some times is problem

4 Likes

last mainline uboot images for krescue was fixed

https://dl.khadas.com/Firmware/uboot/mainline/Khadas.UBOOT.mainline.emmc.kresq

sorry its was my fault (was uploaded broken images ) - NOW this problem was FIXED

PS: plz clean old image or just clean/format dump partition

mainline uboot can get some problem with usb SSD

if not enough power - for ssd we can get freezes
problem will be fixed soon

1 Like

Yes I trust you that it works fine, but it doesn’t on my device where the emmc is erased completely so there is nothing inside.

I can try the latest krescue image and see if that helps.

Thanks for testing things for me.

Where is the updated krescue image for sd card? There is no update on dl.khadas.com

https://dl.khadas.com/Firmware/Krescue/dump/
https://dl.khadas.com/Firmware/Krescue/images/

1 Like

Thanks for the update.
I will try this now.

Hi @hyphop
Vim1 can boot from sdcard with mainline uboot without the need of TST mode but VIm2 needs TST mode for every boot, Is there any ways to make it boot directly with need of TST mode ?

Any plan to getting to to boot without clean emmc ?

I will be releasing Vim images for our 20.08 images mostly for VIm1, vim2 and vim3, If you can take it and make it into kresq image but only if you do it separate image for each device as we manage separate packages for for each device.

Thanks.

i still don’t understand your problem
and try to clarify again :wink:

  1. normal boot sequence for all amlogic devices VIM1 VIM2 VIM3 VIM3L is emmc → sd ( spi fplash excluded ), emmc always is first and only if cant boot from emmc device trying bootup from sd
  2. if we are using mainline uboot on emmc / sd - we have next boot sequence spi → usb → sd → emmc - for bootup linux
  3. sure if we have another uboot on emmc - boot sequence not same
  4. sure sd uboot will be ignore if system was booted from emmc uboot
  5. maskrom mode (TST) work fine only for VIM1 VIM2 EDGE

Any plan to getting to to boot without clean emmc ?

read prev messages

I will be releasing Vim images for our 20.08 images mostly for VIm1, vim2 and vim3, If you can take it and make it into kresq image but only if you do it separate image for each device as we manage separate packages for for each device.

yes its easy i will be return to this task very soon and we can make new manjaro images

BTW: i can write some scripts for easy generation krescue images

3 Likes

@hyphop

Can i boot a coreelec sdcard using mainline uboot ?

  1. u can try
  2. i think yes - but need some modification

I ask because Corelec Documentation states that stock android uboot must be in emmc to boot the coreelec SD/U-Disk.

I tried to boot Coreelec U-Disk using 3-press function key on mainline uboot but it didnt boot into it. Then i converted the U-Disk to fenix Ubuntu mainline and it booted successfully.

Currently I have a running Manjaro on EMMC and dont want to destroy EMMC and only use corelec through U-disk or SD. If you have some free time, please have a look if mainline uboot can boot coreelec with some modification.

Thanks for your efforts and support to khadas users, I really appreciate.

Regards
Yasir

Too much of customization will be needed, have you tried kodi on manjaro?

Coreelec uses legacy proprietary gpu/vpu driver which may or may not work with mainline uboot.

If you still want to use it then flash Android on emmc and flash Manjaro on 1 sd card and coreelc on another sd card. Use the cards when you want to switch os.

Good luck

2 Likes

Hi @Spikerguy

Thanks for the suggestion. I had earlier tried kodi on linux-vim and X11 however performance was very bad. Right now i tried kodi-wayland 19.0 again on linux-rc and mesa-git and seems to be much much faster. The UI is smooth now so maybe I’ll stick with it. I just wanted to check if Coreelec is something else than a glorified KODI or not. In Manjaro, at SDDM we have option to log in directly to KODI, I think that makes it effectively a Core/Libre Elec equivalent .

2 Likes

Mainline u-boot for khadas sbc was updated

  • check topic header Mainline u-boot for khadas sbc for more details and features
  • for last krescue Mainline u-boot image possible write without rewrite exist partition
    (its mean not destructive for emmc installed system - just update uboot area - (not for android)) + before use it please update your krescue to last version - Index of /Firmware/Krescue

meta usage example

curl https://dl.khadas.com/Firmware/uboot/main-line/VIM1.u-boot.sd.bin.meta

##UBOOT_META##
FILE: VIM1.u-boot.sd.bin
UBOOT_VER: 2021.01+
UBOOT_SIZE:    1163776
ENV_OFFSET:    1228800
ENV_SIZE:      32768
SIZE_WITH_ENV: 1261568
MD5: dbf5f960b7f231833640ac12c9693679
DATE: Tue, 27 Apr 2021 12:33:58 +0800
TIME: 1619498038
GIT_COM_ID: 390039c6f5b33e11f00546a3428be88c7edd84a0
GIT_COM_TAG: 0.10
GIT_DOWNLOAD: https://github.com/khadas/khadas-uboot/releases/tag/0.10
GIT_PAGE: https://github.com/khadas/khadas-uboot
DOWNLOAD_LAST: https://dl.khadas.com/Firmware/uboot/mainline/
##UBOOT-META##
##UBOOT##END#
4 Likes