VIM3L SAR ADC Driver writing to serial!

quatro · November 20, 2019, 7:51pm

Hi, I have a specialized communication running on my serial /dev/ttyS0 in the VIM3L… And when I enable the SAR ADC buffer mode (echo 1 > /sys/devices/platform/ff809000.saradc/iio:device0/buffer/enable ) I start to get a lot of undesired communication going on /dev/ttyS0…

Steps to reproduce:

Add a SAR ADC channel to process: echo 1 > /sys/devices/platform/ff809000.saradc/iio:device0/scan_elements/in_voltage0_en
Start ADC periodic sampling: echo 1 > /sys/devices/platform/ff809000.saradc/iio:device0/buffer/enable

Why is it happening? How can I fix this?
@Frank @numbqq

Thanks

numbqq · November 21, 2019, 1:42am

Do you mean something like this ?

[  851.048158@3] iio iio:device0: ADC chnl reg have no valid sampling data
[  851.080163@3] iio iio:device0: ADC chnl reg have no valid sampling data
[  851.112161@3] iio iio:device0: ADC chnl reg have no valid sampling data
[  851.144160@3] iio iio:device0: ADC chnl reg have no valid sampling data
[  851.176162@3] iio iio:device0: ADC chnl reg have no valid sampling data

quatro · November 21, 2019, 1:44am

exactly that!

how can I fix it?

numbqq · November 21, 2019, 1:46am

Hello @quatro

I need to check with this issue…

quatro · November 21, 2019, 1:47am

Ok… please hit me up when you have the fix… thanks!

numbqq · November 21, 2019, 2:15am

Hello @quatro

I’m not sure what you want to do exactly with the ADC…

I check the ADC CH0, CH2 and CH3, I don’t need any setup, I can read the ADC raw data correctly.

# cat /sys/devices/platform/ff809000.saradc/iio:device0/in_voltage3_mean_raw

quatro · November 21, 2019, 2:25am

That’s not my use case… I need the hardware to sample by buffering, and interrupt my program like gpio, I have this working already, but the ADC is generating those errors, this is a feature of the ADC you can read the S905D manual for reference, so it should work correctly.

numbqq · November 21, 2019, 2:33am

If it already works, you can remove the printed information in kernel.

quatro · November 21, 2019, 3:20am

MMM no, the ADC is not working, only my application is…

numbqq · November 21, 2019, 6:24am

It seeem a usage issue? I checked ADC CH2, it works well.

# echo 1 > /sys/devices/platform/ff809000.saradc/iio:device0/scan_elements/in_voltage2_en
# echo 1 > /sys/devices/platform/ff809000.saradc/iio:device0/buffer/enable

You can try.

For SARADC CH2 is routed to the ADC keypad.

github.com

khadas/linux/blob/khadas-vims-4.9.y/arch/arm64/boot/dts/amlogic/kvim3l_linux.dts#L392


		compatible = "amlogic, gpio_keypad";
		status = "okay";
		scan_period = <20>;
		key_num = <1>;
		key_name = "power";
		key_code = <116>;
		key-gpios = <&gpio_ao  GPIOAO_7  GPIO_ACTIVE_HIGH>; /* GPIOAO_7 */
		detect_mode = <0>;/*0:polling mode, 1:irq mode*/
	};


	adc_keypad {
		compatible = "amlogic, adc_keypad";
		status = "okay";
		key_name = "home";
		key_num = <1>;
		io-channels = <&saradc SARADC_CH2>;
		io-channel-names = "key-chan-2";
		key_chan = <SARADC_CH2 SARADC_CH2 SARADC_CH2>;
		key_code = <102>;
		key_val = <108>; //val=voltage/1800mV*1023
		key_tolerance = <40>;

Maybe you can follow the usage of the ADC keypad.

quatro · November 21, 2019, 10:24am

mmm no, that’s because the keypads are accesing the driver periodically and are not registered to the FIFO, causing a misalignment in the buffer channels interleaving… maybe if I add them to the scan it will work…

quatro · November 21, 2019, 10:30am

An yeeeeah! I was right… thanks to your info I could think the misalignment issue… thanks! solved as I thought by adding channel 2 to the scan lines. Every channel to be queried should be added, if not, it will throw an error because the data is not being collected for the channel being asked, under buffer mode.

Did I made it clear in my explanation?

Complete solution:

Add ALL ADC channels which will access the driver (including Channel 2 for Khadas keypad):
echo 1 > /sys/devices/platform/ff809000.saradc/iio:device0/scan_elements/in_voltageX_en
Start ADC periodic sampling:
echo 1 > /sys/devices/platform/ff809000.saradc/iio:device0/buffer/enable

Thanks again! Mark as solved please

quatro · November 22, 2019, 12:03am

How can I make the complete OS not to printk to ttyS0, but ttyS1 instead?

numbqq · November 22, 2019, 1:25am

Edit /boot/boot.ini remove console=ttyS0,115200n8 console=tty0 and add console=tty1.

For full build, you can try this patch:

diff --git a/config/bootscripts/aml_boot.ini b/config/bootscripts/aml_boot.ini
index 9bde578..9b62d49 100644
--- a/config/bootscripts/aml_boot.ini
+++ b/config/bootscripts/aml_boot.ini
@@ -122,7 +122,7 @@ for dev in ${devs}; do
                                                        setenv condev "console=ttyAML0,115200n8 console=tty0 no_console_suspend consoleblank=0";
                                                else
                                                        echo "Booting legacy kernel...";
-                                                       setenv condev "console=ttyS0,115200n8 console=tty0 no_console_suspend consoleblank=0";
+                                                       setenv condev "console=tty1 no_console_suspend consoleblank=0";
                                                fi;
 
                                                fdt addr ${dtb_loadaddr};

quatro · November 22, 2019, 6:57am

I have done the edit, and it works, but not from the beginning of the boot sequence… it sends stuff to the serial S0 until a couple of seconds

numbqq · November 22, 2019, 7:10am

This just disable the output of the kernel stage.

The u-boot and blobs before u-boot will still print messages.

quatro · November 22, 2019, 7:44am

where can I do that? which file?

numbqq · November 22, 2019, 8:13am

You can’t disable them completely. For the close source blobs before u-boot, you can’t disable the printed information.

E.g. These information you can’t disable.

G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:0;READ:0;0.
bl2_stage_init 0x01
bl2_stage_init 0x81
hw id: 0x0000 - pwm id 0x01
bl2_stage_init 0xc1
bl2_stage_init 0x02

L0:00000000
L1:20000703
L2:00008067
L3:14000000
B2:00402000
B1:e0f83180

TE: 160807

BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz

Board ID = 8
Set A53 clk to 24M
Set A73 clk to 24M
Set clk81 to 24M
A53 clk: 1200 MHz
A73 clk: 1200 MHz
CLK81: 166.6M
smccc: 0002bc04
eMMC boot @ 0
sw8 s
DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
board id: 8
Load FIP HDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0
fw parse done
Load ddrfw from eMMC, src: 0x00060200, des: 0xfffd0000, size: 0x0000c000, part: 0
Load ddrfw from eMMC, src: 0x00038200, des: 0xfffd0000, size: 0x00004000, part: 0
PIEI prepare done
fastboot data load
00000000
emmc switch 1 ok
ddr saved addr:00016000
Load ddr parameter from eMMC, src: 0x02c00000, des: 0xfffd0000, size: 0x00001000, part: 0
00000000
emmc switch 0 ok
fastboot data verify
verify result: 265
Cfg max: 4, cur: 1. Board id: 255. Force loop cfg
LPDDR4 probe
ddr clk to 1608MHz
Load ddrfw from eMMC, src: 0x0003c200, des: 0xfffd0000, size: 0x0000c000, part: 0

dmc_version 0001
Check phy result
INFO : End of CA training
INFO : End of initialization
INFO : Training has run successfully!
Check phy result
INFO : End of initialization
INFO : End of read enable training
INFO : End of fine write leveling
INFO : End of Write leveling coarse delay
INFO : Training has run successfully!
Check phy result
INFO : End of initialization
INFO : End of read dq deskew training
INFO : End of MPR read delay center optimization
INFO : End of write delay center optimization
INFO : End of read delay center optimization
INFO : End of max read latency training
INFO : Training has run successfully!
1D training succeed
Load ddrfw from eMMC, src: 0x00048200, des: 0xfffd0000, size: 0x0000c000, part: 0
Check phy result
INFO : End of initialization
INFO : End of 2D read delay Voltage center optimization
INFO : End of 2D read delay Voltage center optimization
INFO : End of 2D write delay Voltage center optimization
INFO : End of 2D write delay Voltage center optimization
INFO : Training has run successfully!

channel==0
RxClkDly_Margin_A0==97 ps 10
TxDqDly_Margin_A0==106 ps 11
RxClkDly_Margin_A1==97 ps 10
TxDqDly_Margin_A1==106 ps 11
TrainedVREFDQ_A0==26
TrainedVREFDQ_A1==26
VrefDac_Margin_A0==28
DeviceVref_Margin_A0==26
VrefDac_Margin_A1==26
DeviceVref_Margin_A1==26


channel==1
RxClkDly_Margin_A0==97 ps 10
TxDqDly_Margin_A0==106 ps 11
RxClkDly_Margin_A1==87 ps 9
TxDqDly_Margin_A1==116 ps 12
TrainedVREFDQ_A0==26
TrainedVREFDQ_A1==26
VrefDac_Margin_A0==26
DeviceVref_Margin_A0==25
VrefDac_Margin_A1==26
DeviceVref_Margin_A1==25

 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004 

soc_vref_reg_value 0x 00000028 00000027 00000026 00000026 00000026 00000027 00000027 00000025 00000028 00000026 00000027 00000029 00000026 00000026 00000024 00000024 00000028 00000027 00000025 00000026 00000024 00000027 00000026 00000026 00000026 00000026 00000024 00000028 00000025 00000025 00000027 00000025 dram_vref_reg_value 0x 00000014
2D training succeed
aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
auto size-- 65535DDR cs0 size: 2048MB
DDR cs1 size: 2048MB
DMC_DDR_CTRL: 00e00024DDR size: 3928MB
cs0 DataBus test pass
cs1 DataBus test pass
cs0 AddrBus test pass
cs1 AddrBus test pass

100bdlr_step_size ps== 457
result report
boot times 0Enable ddr reg access
00000000
emmc switch 3 ok
Authentication key not yet programmed
get rpmb counter error 0x00000007
00000000
emmc switch 0 ok
Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
Load BL3X from eMMC, src: 0x00078200, des: 0x01768000, size: 0x000c8000, part: 0
0.0;M3 CHK:0;cm4_sp_mode 0
MVN_1=0x00000000
MVN_2=0x00000000
[Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
OPS=0x10
ring efuse init
chipver efuse init
29 0b 10 00 01 1c 09 00 00 02 37 30 4e 42 4e 50 
[0.018961 Inits done]
secure task start!
high task start!
low task start!
run into bl31
NOTICE:  BL31: v1.3(release):4fc40b1
NOTICE:  BL31: Built : 15:58:17, May 22 2019
NOTICE:  BL31: G12A normal boot!
NOTICE:  BL31: BL33 decompress pass
ERROR:   Error initializing runtime service opteed_fast

quatro · November 22, 2019, 11:54pm

mmm… I don’t mind if they print to the console or dmesg, I need to remove it from sending info tothe serial pins of the board (18 and 19)

numbqq · November 25, 2019, 1:14am

They will be send to the serial pins by default, we can’t change it, we don’t have the source code.