Add support of MAX98091 codec to Edge (Pi)

Hello,

I want to add the support of MAX98091 codec in the Edge-Pi. I saw that Edge-pi has the driver of MAX98090 which is compatible with MAX98091. So, I hope I don’t have to do much but my concern is with device tree entry. How do I create a node for my codec and which gpios will I have to use from Edge V GPIO Pin-outs? I see few I2S0 lines which I think will be required to transfer the audio signal but not aware which to select.

Also, what is the functionality of ‘2S0_LRCK_TX/GPIO3_D2’ line? Or there is I2S0 instead of 2S0!!

Thanx.

Hi @Parth
You can refer the Captain Schematic for your design:

Rockchip SoC use TX & RX total two PINs for LRCK.

@Gouwa
I am sharing my hardware connections of Khadas Edge V to MAX98091. So, will you please have a look at it?
I want to confirm whether my connections are okay or not.

Yes, checked, I think it’s okay.

Just be note to follow the reference design to connecto the TX/RX pins.

Good day!

1 Like

I have shorted LRCK_TX and LRCK_RX pins of khadas board and then it is given to MAX98091 LRCLK pin.

You might need the 33R or similar value registor for better signal quality.

Thanx.

One more thing. I am sharing my device tree entry for max98091. Would you please have a look at it?
I am getting an error from rockchip-max98090.c file.

DTS Entry:

sound {
status = “okay”;
compatible = “rockchip,rockchip-audio-max98090”;
rockchip,model = “ROCKCHIP-I2S”;
pinctrl-names = “default”;
rockchip,i2s-controller = <&i2s0>;
rockchip,audio-codec = <&max98091>;
};

max98091: max98091@10 {
compatible = “maxim,max98091”;
reg = <0x10>;
clocks = <&cru SCLK_I2S_8CH_OUT>;
clock-names = “mclk”;
#sound-dai-cells = <1>;
interrupt-parent = <&gpio1>;
interrupts = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
pinctrl-names = “default”;
pinctrl-0 = <&max98091_irq>;
};

max98091 {
max98091_irq: max98091_irq {
rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>; /* GPIO1_B7 */
};

@Terry or @goenjoy may help you out.

@Gouwa

Thank You. I really appreciate this.