Where can I find the source code of BL2

VIM4
1

Which system do you use? Android, Ubuntu, OOWOW or others?

Unubtu 22.04

Which version of system do you use? Khadas official images, self built images, or others?

Khadas official

Please describe your issue below:

I’m using VIM4 + Ubuntu 22.04.
The initialization of LPDDR4x and training do in BL2 ?
Then where can I find the source code of BL2…?
I’d like to see the source code.
Please teach me.

Post a console log of your issue below:


T7:BL:055c20;ID:9056601109611515;FEAT:30F:1FFF0000:B002F:1;......

Bl2_early_platform_setup: indicates bl2ex flow!

OTP_LIC00 : 0f0300000000ff1f2f000b0000000000
OTP_LIC10 : 008207000001fc000c00001000000300
OTP_LIC20 : ffffffbfffff0700ff80008003000003
OTP_LIC30 : 00000002010000008f03000203000000

TE: 303354

BL2 Built : 17:12:14, May  5 2022. t7 origin/master gcad8fc9 - jenkins@walle02-sh

Board ID = 5
Set sys clock to 24Mhz
syspll is 1512Mhz. Locked
sys1pll is 1608Mhz. Locked
Set sys clock to 167Mhz
gp0pll is 0Mhz. Locked
bl2_platform_setup
boot area list: 
1STBLOB	00000200	00040000
BL2E	00040200	00013000
BL2X	00053200	00011000
DDRFIP	00064200	00040000
DEVFIP	000a4200	00300000
s_setup from rom:00010081
dma mode
derive RSPK OK
DDR driver_vesion: AML_S_PHY_T7_1_16 build time: May  5 2022 17:12:08
ddr id: 0

ddr clk to 2016MHz
PIEI done
Cfg max: 2, cur: 1. Board id: 255. Force loop cfg

LPDDR4 probe

ddr clk to 2016MHz
Check phy result
INFO : End of CA training
INFO : End of initialization
INFO : Training has run successfully!
Check phy result
2

@cuckoo933 This part is not open source from the vendor, so you can’t get the source code.We don’t have the source code either

3

OK, I understand what you mean.

I have two more question.

  1. Is it correct to do LPDDR4 initialization and training in BL2?
  2. If a fail occurs in LPDDR4 training and cannot go to Uboot, what kind of problem should it be considered?
DDR driver_vesion: AML_S_PHY_T7_1_16 build time: May  5 2022 17:12:08
ddr id: 0

ddr clk to 2016MHz
PIEI done
Cfg max: 2, cur: 1. Board id: 255. Force loop cfg

LPDDR4 probe

ddr clk to 2016MHz
Check phy result
INFO : ERROR : Training has failed!
Check phy result
INFO : End of initialization
INFO : End of read enable training
INFO : End of fine write leveling
INFO : ERROR : Training has failed!
ch0 1D training failed
4

Yes.

You change the DDR hardware? We don’t provide support for DDR turning.

5

Yes, I changed LPDDR4x from two 32Gb(2CSx2CH) devices to two 16Gb(1CSx2CH) devices for test.
And I know you don’t support these kind of HW change issue.
I just need some simple advice where to look if possible.

Additionally I have a question in your schematic.
What’s the purpose of the DDR_ID signal below ?
VIM4 software check things like DDR manufacturer ID?
So, if the IDs are different, then the DDR doesn’t work?
image