VIM3L starts, u-boot starts. However, in the serial console, the last output is:
vpp_init
Anyone familiar with such a behavior?
Which Khadas SBC do you use?
VIM3L
Which version of system do you use? Khadas official images, self built images, or others?
Tried VIM3L_Ubuntu-gnome-focal_Linux-4.9_arm64_EMMC_V1.0.9-211217 and VIM3L_Pie_V211220
Please describe your issue below:
I managed to flash EEMC using the USB burning tool. It sucessfully erased and flashed the device.
So I assume, that the hardware is kinda OK.
However, after boot, the VIM3L outputs up to vpp_init on the serial console and that’s it.
Tried also with different power supplies, USB-cables and so on. Always the same behavior.
I could not find any useful information by googling. Maybe somebody has a hint, what could be the problem? That would be nice!
Console log:
1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:F;RCY:0;EMMC:0;READ:0;0.0;CHK:0;
bl2_stage_init 0x01
bl2_stage_init 0x81
hw id: 0x0000 - pwm id 0x01
bl2_stage_init 0xc1
bl2_stage_init 0x02
L0:00000000
L1:00000703
L2:00008067
L3:15000000
S1:00000000
B2:20282000
B1:a0f83180
TE: 140303
BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
Board ID = 8
Set cpu clk to 24M
Set clk81 to 24M
Use GP1_pll as DSU clk.
DSU clk: 1200 Mhz
CPU clk: 1200 MHz
Set clk81 to 166.6M
eMMC boot @ 0
sw8 s
DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
board id: 8
Load FIP HDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0
fw parse done
Load ddrfw from eMMC, src: 0x00060200, des: 0xfffd0000, size: 0x0000c000, part: 0
Load ddrfw from eMMC, src: 0x00038200, des: 0xfffd0000, size: 0x00004000, part: 0
PIEI prepare done
fastboot data load
00000000
emmc switch 1 ok
ddr saved addr:00016000
Load ddr parameter from eMMC, src: 0x02c00000, des: 0xfffd0000, size: 0x00001000, part: 0
00000000
emmc switch 0 ok
fastboot data verify
verify result: 265
Cfg max: 4, cur: 1. Board id: 255. Force loop cfg
LPDDR4 probe
ddr clk to 1608MHz
Load ddrfw from eMMC, src: 0x0003c200, des: 0xfffd0000, size: 0x0000c000, part: 0
dmc_version 0001
Check phy result
INFO : ERROR : Training has failed!
1D training failed
Cfg max: 4, cur: 2. Board id: 255. Force loop cfg
LPDDR4 probe
ddr clk to 1608MHz
Load ddrfw from eMMC, src: 0x0003c200, des: 0xfffd0000, size: 0x0000c000, part: 0
dmc_version 0001
Check phy result
INFO : ERROR : Training has failed!
1D training failed
Cfg max: 4, cur: 2. Board id: 255. Force loop cfg
LPDDR4 probe
ddr clk to 1608MHz
Load ddrfw from eMMC, src: 0x0003c200, des: 0xfffd0000, size: 0x0000c000, part: 0
dmc_version 0001
Check phy result
INFO : End of CA training
INFO : End of initialization
INFO : Training has run successfully!
Check phy result
INFO : End of initialization
INFO : End of read enable training
INFO : End of fine write leveling
INFO : End of Write leveling coarse delay
INFO : Training has run successfully!
Check phy result
INFO : End of initialization
INFO : End of read dq deskew training
INFO : End of MPR read delay center optimization
INFO : End of write delay center optimization
INFO : End of read delay center optimization
INFO : End of max read latency training
INFO : Training has run successfully!
1D training succeed
Load ddrfw from eMMC, src: 0x00048200, des: 0xfffd0000, size: 0x0000c000, part: 0
Check phy result
INFO : End of initialization
INFO : End of 2D read delay Voltage center optimization
INFO : End of 2D read delay Voltage center optimization
INFO : End of 2D write delay Voltage center optimization
INFO : End of 2D write delay Voltage center optimization
INFO : Training has run successfully!
channel==0
RxClkDly_Margin_A0==77 ps 8
TxDqDly_Margin_A0==106 ps 11
RxClkDly_Margin_A1==0 ps 0
TxDqDly_Margin_A1==0 ps 0
TrainedVREFDQ_A0==30
TrainedVREFDQ_A1==0
VrefDac_Margin_A0==28
DeviceVref_Margin_A0==30
VrefDac_Margin_A1==0
DeviceVref_Margin_A1==0
channel==1
RxClkDly_Margin_A0==97 ps 10
TxDqDly_Margin_A0==97 ps 10
RxClkDly_Margin_A1==0 ps 0
TxDqDly_Margin_A1==0 ps 0
TrainedVREFDQ_A0==28
TrainedVREFDQ_A1==0
VrefDac_Margin_A0==24
DeviceVref_Margin_A0==28
VrefDac_Margin_A1==0
DeviceVref_Margin_A1==0
dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
soc_vref_reg_value 0x 00000025 00000024 00000026 00000027 00000025 00000026 00000027 00000024 00000024 00000024 00000026 00000025 00000025 00000025 00000025 00000026 00000028 00000027 00000027 00000027 00000027 00000026 00000027 00000027 00000026 00000029 00000026 00000027 00000026 00000026 00000026 00000025 dram_vref_reg_value 0x 00000013
2D training succeed
aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:53:31
auto size-- 65535DDR cs0 size: 2048MB
DDR cs1 size: 0MB
DMC_DDR_CTRL: 00c0002cDDR size: 2048MB
cs0 DataBus test pass
cs0 AddrBus test pass
100bdlr_step_size ps== 403
result report
boot times 0Enable ddr reg access
00000000
emmc switch 3 ok
Authentication key not yet programmed
get rpmb counter error 0x00000007
00000000
emmc switch 0 ok
Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
Load BL3X from eMMC, src: 0x00078200, des: 0x01768000, size: 0x000cc000, part: 0
bl2z: ptr: 05129330, size: 00001e40
0.0;M3 CHK:0;cm4_sp_mode 0
MVN_1=0x00000000
MVN_2=0x00000000
[Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
OPS=0x04
ring efuse init
2b 0c 04 00 01 26 31 00 00 06 34 39 39 46 38 50
[0.017354 Inits done]
secure task start!
high task start!
low task start!
run into bl31
NOTICE: BL31: v1.3(release):4fc40b1
NOTICE: BL31: Built : 15:57:33, May 22 2019
NOTICE: BL31: G12A normal boot!
NOTICE: BL31: BL33 decompress pass
ERROR: Error initializing runtime service opteed_fast
U-Boot 2015.01 (Dec 17 2021 - 18:21:21)
DRAM: 2 GiB
Relocation Offset is: 76e4c000
spi_post_bind(spifc): req_seq = 0
register usb cfg[0][1] = 0000000077f32410
aml_i2c_init_port init regs for 0
MCU version: 0x00 0x03
MCU version is to low! Doesn't support froce boot from SD card.
MMC: aml_priv->desc_buf = 0x0000000073e3ce50
aml_priv->desc_buf = 0x0000000073e3f190
SDIO Port B: 0, SDIO Port C: 1
co-phase 0x2, tx-dly 0, clock 400000
co-phase 0x2, tx-dly 0, clock 400000
co-phase 0x2, tx-dly 0, clock 400000
emmc/sd response timeout, cmd8, status=0x3ff2800
emmc/sd response timeout, cmd55, status=0x3ff2800
co-phase 0x2, tx-dly 0, clock 400000
co-phase 0x2, tx-dly 0, clock 40000000
aml_sd_retry_refix[983]:delay = 0x0,gadjust =0x172000
[mmc_startup] mmc refix success
init_part() 297: PART_TYPE_AML
[mmc_init] mmc init success
start dts,buffer=0000000073e41a00,dt_addr=0000000073e41a00
get_partition_from_dts() 91: ret 0
parts: 3
00: logo 0000000000800000 1
01: ramdisk 0000000002000000 1
02: rootfs ffffffffffffffff 4
init_part() 297: PART_TYPE_AML
eMMC/TSD partition table have been checked OK!
crc32_s:0x1577dad == storage crc_pattern:0x1577dad!!!
crc32_s:0xee152b83 == storage crc_pattern:0xee152b83!!!
crc32_s:0x79f50f07 == storage crc_pattern:0x79f50f07!!!
mmc env offset: 0x6c00000
In: serial
Out: serial
Err: serial
reboot_mode=cold_boot
[store]To run cmd[emmc dtb_read 0x1000000 0x40000]
_verify_dtb_checksum()-3477: calc 8d426457, store 8d426457
_verify_dtb_checksum()-3477: calc 8d426457, store 8d426457
dtb_read()-3694: total valid 2
update_old_dtb()-3675: do nothing
aml_i2c_init_port init regs for 0
fusb302_init: Device ID: 0x91
CC connected in 1 as UFP
fusb302 detect chip.port_num = 0
amlkey_init() enter!
[EFUSE_MSG]keynum is 1
vpu: clk_level in dts: 7
vpu: vpu_power_on
vpu: set clk: 666667000Hz, readback: 666666667Hz(0x100)
vpu: vpu_module_init_config
vpp: vpp_init