VIM3L S905D3 L1,L2,L3 cache size / way?


请问有人知道VIM3L S905D3的L1,L2,L3 Cache各自的大小与Way数吗?


Does anyone know the respective size and Way number of the L1, L2, and L3 Cache of VIM3L S905D3?

@HappyFamily l1 cache is 32Kb for each core, l2 cache is unknown, and l3 cache is system unified (for exact, contact khadas team)

you can get this from the S905D3 datasheet.

good day!

Thank you for your information.
I looked up S905D3 datasheet.
But I only found out below parameter.

L1 : I/D 32KB , way unknown (for each core)
L2 : unknown , way unknown
L3 : unknown , way unknown

I have contact kdahas team for support.
Thank you very much !!

Hope you had a great weekend,

Unfortunately, Amlogic is rather tight-lipped about specifications (and have a history of lying about some of what they do say). There are architectural registers for the cores that will give you this info but they’re only accessible from EL1 (kernel mode) and only cover the L1 and L2 caches which are part of the Cortex-A55 core itself. L3 (or L2 if they configured no core-based L2 like in the A311D is a crapshoot (if it even exists)).

Good luck, and please share if you find out!


Thanks for your information about register.
I got some below information,
It seems no L2-cache in S905D3.

Get VIM3L L1 D-Cache
CSSELR_EL1 : [0x00000000]
CCSIDR_EL1 : [0x700fe01a] (32KB, 4 way-set associative)

Get VIM3L L1 I-Cache
CSSELR_EL1 : [0x00000001]
CCSIDR_EL1 : [0x200fe01a] (32KB, 4 way-set associative)

Get VIM3L L2 Cache
CSSELR_EL1 : [0x00000002]
CCSIDR_EL1 : [0x703fe07a] (512KB, 16 way-set associative)

Get VIM3L L3 Cache
CSSELR_EL1 : [0x00000000] (Set 0x4, Get 0x0, It seems no L2.)
CCSIDR_EL1 : [0x700fe01a]

(If the register parameter is trusted…XD)

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Good to know! I believe the L1/L2 registers are set in the processor IP configuration and can’t be changed by low-level licensees but you never know for sure; that stuff is a closely guarded ARM secret. Thanks for finding this out!

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@HappyFamily nice to see you got it…
understandably by the more cruder way xD

If the company won’t tell you, just ask the chip! :smiley:

that still isn’t true sometimes,
like amlogic did before with their chips, spoofing the system clockspeed.
but this is the last straw ¯ \ _ (ツ) _ / ¯

True and I wouldn’t put it past them to do it again either. They cheaped out on the A311D, too; the L2 cache (which would be part of the processor IP and per-cluster) is technically zero and they just have a chunk of unified L3.

Thanks everyone for your assistance! :smiling_face_with_three_hearts: :heart_eyes: :100: :+1: :+1: :+1: :+1: :+1: :+1: :handshake: :handshake: :handshake: :handshake: :handshake:
It is my honor to cooperate with you.
Benefited me a lot.


Happy to help, and have a great day!

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