VIM3L: pcie mapping BAR1 of size 4MB

VIM3
1

Hi,

I am using a pcie device which has a BAR1 size of 4MB.
In the device driver I’m using ‘ioremap’ to map this 4MB to kernel virtual address.
ioremap is succeeding and is not returning any failure.
However If I write any data beyond 1MB into the BAR1 space, and read back the same
I’m reading only 0xffff. Any data written/read in the first 1MB of BAR1 space is fine.
Is there any limitation in VIM3L or the amlogic-v2 pcie driver where only 1MB of BAR1 mapping is allowed ?

I’m using the 4.9 kernel checked out using the instructions from - https://docs.khadas.com/vim3/DownloadAndroidSourceCode.html

2

Dmesg logs:

[ 1.467252] amlogic-pcie-v2 fc000000.pcieA: amlogic_pcie_probe!
[ 1.475256] OF: PCI: host bridge /pcieA@fc000000 ranges:
[ 1.478160] OF: PCI: IO 0xfc600000…0xfc6fffff -> 0x00000000
[ 1.484305] OF: PCI: MEM 0xfc700000…0xfdffffff -> 0xfc70000000000000
[ 1.492384] amlogic-pcie-v2 fc000000.pcieA: Set the RC Bus Master, Memory Space and I/O Space enables.
[ 1.500637] amlogic-pcie-v2 fc000000.pcieA: normal gpio
[ 1.506104] amlogic-pcie-v2 fc000000.pcieA: GPIO normal: amlogic_pcie_assert_reset
[ 1.522757] amlogic-pcie-v2 fc000000.pcieA: PCIE SPEED IS GEN2
[ 1.523121] amlogic-pcie-v2 fc000000.pcieA: link up
[ 1.528420] amlogic-pcie-v2 fc000000.pcieA: PCI host bridge to bus 0000:00
[ 1.535308] pci_bus 0000:00: root bus resource [bus 00-ff]
[ 1.540989] pci_bus 0000:00: root bus resource [io 0x0000-0xfffff]
[ 1.547488] pci_bus 0000:00: root bus resource [mem 0xfc700000-0xfdffffff] (bus address [0x00000000-0x018fffff])
[ 1.557906] amlogic-pcie-v2 fc000000.pcieA: the device class is not reported correctly from the register
[ 1.567610] pci 0000:00:00.0: [16c3:abcd] type 01 class 0x060400
[ 1.567640] pci 0000:00:00.0: reg 0x38: [mem 0xfc700000-0xfc70ffff pref]
[ 1.567690] pci 0000:00:00.0: supports D1
[ 1.567695] pci 0000:00:00.0: PME# supported from D0 D1 D3hot D3cold
[ 1.567960] PCI: bus0: Fast back to back transfers disabled
[ 1.573556] pci 0000:01:00.0: [14e4:4441] type 00 class 0x028000
[ 1.573648] pci 0000:01:00.0: reg 0x10: [mem 0xfc700000-0xfc70ffff 64bit]
[ 1.573707] pci 0000:01:00.0: reg 0x18: [mem 0xfc700000-0xfcafffff 64bit]
[ 1.573830] pci 0000:01:00.0: Max Payload Size set to 256 (was 128, max 512)
[ 1.580978] pci 0000:01:00.0: supports D1 D2
[ 1.580984] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
[ 1.592731] PCI: bus1: Fast back to back transfers disabled
[ 1.592960] pci 0000:00:00.0: BAR 8: assigned [mem 0xfc800000-0xfcdfffff]
[ 1.599855] pci 0000:00:00.0: BAR 6: assigned [mem 0xfc700000-0xfc70ffff pref]
[ 1.607330] pci 0000:01:00.0: BAR 2: assigned [mem 0xfc800000-0xfcbfffff 64bit]
[ 1.614839] pci 0000:01:00.0: BAR 2: error updating (0x100004 != 0x000004)
[ 1.621921] pci 0000:01:00.0: BAR 0: assigned [mem 0xfcc00000-0xfcc0ffff 64bit]
[ 1.629488] pci 0000:00:00.0: PCI bridge to [bus 01-ff]
[ 1.634861] pci 0000:00:00.0: bridge window [mem 0xfc800000-0xfcdfffff]

Looks like there is an error while updating BAR 2 mapping (BAR 1 of endpoint).
Is there some limitation on not mapping 4MB size ?

3

No idea, but the size is 10+ MB, not only 1MB.

4

Hello @kykishore

Have you resolved this issue?

There is a patch maybe can resolve your issue:

diff --git a/arch/arm64/boot/dts/amlogic/mesonsm1.dtsi b/arch/arm64/boot/dts/amlogic/mesonsm1.dtsi
index 1493f6a5258a..a9026bc42358 100644
--- a/arch/arm64/boot/dts/amlogic/mesonsm1.dtsi
+++ b/arch/arm64/boot/dts/amlogic/mesonsm1.dtsi
@@ -920,9 +920,9 @@
                interrupt-map-mask = <0 0 0 0>;
                interrupt-map = <0 0 0 0 &gic GIC_SPI 223 IRQ_TYPE_EDGE_RISING>;
                device_type = "pci";
-               ranges = <0x81000000 0 0 0 0xfc600000 0x0 0x100000
+               ranges = <0x81000000 0 0 0 0xfc600000 0x0 0x400000
                        /* downstream I/O */
-                       0x82000000 0 0xfc700000 0x0 0xfc700000 0 0x1900000>;
+                       0x82000000 0 0xfca00000 0x0 0xfca00000 0 0x1600000>;
                        /* non-prefetchable memory */
                num-lanes = <1>;
                pcie-num = <1>;
5

Thanks for the update.
This patch seems to be for 64 bit kernel ?

I am building using the instructions in https://docs.khadas.com/vim3/BuildAndroid.html
and it is building only 32 bit kernel.
Could you please share on how to build 64 bit kernel for the same source code in
https://docs.khadas.com/vim3/DownloadAndroidSourceCode.html

Anyway I applied the patch to the 32 bit dts file -
arch/arm/boot/dts/amlogic/mesonsm1.dtsi
and built the kernel and re-tested.
However now ‘lspci’ does not show any devices.
If I remove the patch ‘lspci’ again shows my device.

6

is it possible that set the size of non-prefetchable memory from 0x1600000 to 0xA000000 which is what I need for larger bar size?

Or it is possible to move the whole pcie from fc000000 to f0000000?