Vim3l briked after injecting bl301 from coreelec

Which Khadas SBC do you use?

VIM3L

Which system do you use? Android, Ubuntu, OOWOW or others?

Android, CoreELEC

Which version of system do you use? Khadas official images, self built images, or others?

Khadas official images

Please describe your issue below:

After injecting the BL301

The system was blocked in a continuous booting loop.
I created an SD card with Burn Card Maker Tool with latest android image “VIM3L_Pie_V211220.7z”
I put VIM3L in TST Mode by pushing the function key 3 times but
on serial interface I could see that the sdcard is ignored and not booting from it.

Can the board still be saved somehow to flash the internal eMMC with correct bootloader without bl301?

Post a console log of your issue below:

SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:D;RCY:0;USB:0;EMMC:0;READ:0;0.0;CHK:0;
bl2_stage_init 0x01
bl2_stage_init 0x81
hw id: 0x0000 - pwm id 0x01
bl2_stage_init 0xc1
bl2_stage_init 0x02

L0:00000000
L1:00000703
L2:00008067
L3:15000000
S1:00000000
B2:20282000
B1:a0f83180

TE: 952514

BL2 Built : 19:23:14, Sep 18 2020. g12a g9fde858 - gongwei.chen@droid11-sz

Board ID = 8
Set cpu clk to 24M
Set clk81 to 24M
Use GP1_pll as DSU clk.
DSU clk: 1200 Mhz
CPU clk: 1200 MHz
Set clk81 to 166.6M
eMMC boot @ 0
sw8 s
board id: 8
Load FIP HDR DDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0
fw parse done
PIEI prepare done
00000000
emmc switch 1 ok
ddr saved addr:00016000
Load ddr parameter from eMMC, src: 0x02c00000, des: 0xfffd0000, size: 0x00001000, part: 0
00000000
emmc switch 0 ok
fastboot data verify
result: 255
Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
LPDDR4 probe

LPDDR4_PHY_V_0_1_22-Built : 14:57:16, Sep 1 2020. g12a g3c95fed - gongwei.chen@droid11-sz
ddr clk to 1608MHz

dmc_version 0001
Check phy result
INFO : ERROR : Training has failed!
Check phy result
INFO : ERROR : Training has failed!
Check phy result
INFO : End of initialization
INFO : ERROR : Training has failed!
1D training failed
Cfg max: 12, cur: 2. Board id: 255. Force loop cfg
LPDDR4 probe
ddr clk to 1608MHz

dmc_version 0001
Check phy result
INFO : End of CA training
INFO : End of initialization
INFO : Training has run successfully!
Check phy result
INFO : End of initialization
INFO : End of read enable training
INFO : End of fine write leveling
INFO : End of read dq deskew training
INFO : End of MPR read delay center optimization
INFO : End of Write leveling coarse delay
INFO : End of read delay center optimization
INFO : Training has run successfully!
Check phy result
INFO : End of initialization
INFO : End of MPR read delay center optimization
INFO : End of write delay center optimization
INFO : End of read delay center optimization
INFO : End of max read latency training
INFO : Training has run successfully!
1D training succeed
Check phy result
INFO : End of initialization
INFO : End of 2D read delay Voltage center optimization
INFO : End of 2D read delay Voltage center optimization
INFO : End of 2D write delay Voltage center optimization
INFO : End of 2D write delay Voltage center optimization
INFO : Training has run successfully!

soc_vref_reg_value 0x 00000028 00000027 00000028 00000028 00000026 00000025 00000027 00000026 00000027 00000026 00000025 00000027 00000026 00000026 00000025 00000027 00000026 00000028 00000025 00000026 00000025 00000028 00000024 00000025 00000025 00000027 00000026 00000028 00000026 00000026 00000025 00000026 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
dram_vref_reg_value 0x 00000013
2D training succeed
auto size-- 65535DDR cs0 size: 2048MB
DDR cs1 size: 0MB
DMC_DDR_CTRL: 00c0002cDDR size: 2048MB
cs0 DataBus test pass
cs0 AddrBus test pass

non-sec scramble use zero key
ddr scramble enabled

100bdlr_step_size ps== 414
result report
boot times 276Enable ddr reg access
00000000
emmc switch 3 ok
Authentication key not yet programmed
get rpmb counter error 0x00000007
00000000
emmc switch 0 ok
Load FIP TMP HDR from eMMC, src: 0x00010200, des: 0x05100000, size: 0x00004000, part: 0
Load BL31 from eMMC, src: 0x00085200, des: 0x05104000, size: 0x00030970, part: 0
bl2z_ptr: 0512d334
img_info->image_base: 05100000
bl2z: ptr: 0512d330, size: 00001e40
jump to BL2z:05200000

BL2Z Built : 17:18:09, Nov 20 2020. g12a gv1.3-137-g5c909a0 - gongwei.chen@droid11-sz

aml log : BL2Z watch dog is disabled!
STACK HEADER:0x05210000
rcf addr:fffaf010, arg:00000000, flag:00000000, ctrl:00000000
reboot reason:0d
CFG:00000000
return to BL2
Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
Load BL3X from eMMC, src: 0x00078200, des: 0x01768000, size: 0x00114000, part: 0
0.0;M3 CHK:0;cm4_sp_mode 0
[Image: g12a_v1.1.3396-c893a7153 2020-11-11 13:54:29 gongwei.chen@droid11-sz]
OPS=0x40
ring efuse init
2b 0b 40 00 01 17 11 00 00 06 34 39 39 46 38 50
[1.889329 Inits done]
1000f000
=== PROCESS EXCEPTION: 05 ====== xPSR: 21000000 ===
r0 :1000e31e r1 :00000020 r2 :ff80300c r3 :00000000
r4 :1000e31d r5 :1000f000 r6 :00000200 r7 :1000d3a4
r8 :00000000 r9 :00000000 r10:00000000 r11:00000000
r12:00000000 sp :1000d340 lr :1000a063 pc :1000a184
Precise data bus error, bfar = 1000e31e
mmfs = 8200, shcsr = 70002, hfsr = 0, dfsr = 0

=========== Process Stack Contents ===========
1000d360: 00000000 1000a063 00000000 00000000
1000d370: 00000000 00000000 00000000 10000a51
1000d380: 00000000 00000000 00000000 00000000
1000d390: 00000000 00000000 00000000 00000000

Rebooting…

I managed to fix it. For some reason any method to boot from sdcard listed in Boot Into Upgrade Mode | Khadas Documentation did not work. Not even M-register mode. The booting was still happening from emmc even if sdcard was OK (Amlogic burn card maker with latest android image Upgrade Android Via An SD-Card | Khadas Documentation). I managed to make emmc unavailable by short circuit the pins 4 (GND) and 7(HOLD) of the emmc chip W25Q128FW just enough to keep it from boot. Then release the short to allow the image to be written on it.

1 Like