I worked normally on CF card (Ubuntu 20.04 server (fenix)). After I have transfer linux to
EMMC by emmc-install command. The system worked correctly long time (with poweroff
command).
Hardware version is: VIM3 V13 2009 22 11
Once VIM3 does not boot after an incorrect power off. On the console I get
repeated log messages (see below). Is it possibe to fix the problem (I don’t want to
lost many settings)?
Is it possible to protect VIM3 from such a problem after an incorrect power off
for the future?
Thank tou for support, please help.
Logs on console:
G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:0;READ:0;0.
bl2_stage_init 0x01
bl2_stage_init 0x81
hw id: 0x0000 - pwm id 0x01
bl2_stage_init 0xc1
bl2_stage_init 0x02
L0:00000000
L1:20000703
L2:00008067
L3:14000000
B2:00402000
B1:e0f83180
TE: 197596
BL2 Built : 19:23:21, Sep 18 2020. g12b g9fde858 - gongwei.chen@droid11-sz
Board ID = 8
Set A53 clk to 24M
Set A73 clk to 24M
Set clk81 to 24M
A53 clk: 1200 MHz
A73 clk: 1200 MHz
CLK81: 166.6M
smccc: 00034cc0
eMMC boot @ 0
sw8 s
board id: 8
Load FIP HDR DDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0
Get wrong ddr fw magic! Error!!
fw parse done
PIEI prepare done
00000000
emmc switch 1 ok
00000000
emmc switch 2 ok
NO find ddr boot_info from eMMC
fastboot data verify
result: 255
Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
LPDDR4 probe
LPDDR4_PHY_V_0_1_22-Built : 14:57:26, Sep 1 2020. g12b g3c95fed - gongwei.chen@droid11-sz
ddr clk to 1608MHz
00000000
emmc switch 0 ok
dmc_version 0001
Check phy result
INFO : End of CA training
INFO : End of initialization
INFO : Training has run successfully!
Check phy result
INFO : End of initialization
INFO : End of read enable training
INFO : End of fine write leveling
INFO : End of read dq deskew training
INFO : End of MPR read delay center optimization
INFO : End of Write leveling coarse delay
INFO : End of read delay center optimization
INFO : Training has run successfully!
Check phy result
INFO : End of initialization
INFO : End of MPR read delay center optimization
INFO : End of write delay center optimization
INFO : End of read delay center optimization
INFO : End of max read latency training
INFO : Training has run successfully!
1D training succeed
Check phy result
INFO : End of initialization
INFO : End of 2D read delay Voltage center optimization
INFO : End of 2D read delay Voltage center optimization
INFO : End of 2D write delay Voltage center optimization
INFO : End of 2D write delay Voltage center optimization
INFO : Training has run successfully!
soc_vref_reg_value 0x 00000024 00000025 00000024 00000025 00000023 00000024 00000024 00000025 00000025 00000025 00000022 00000024 00000025 00000023 00000022 00000024 00000025 00000025 00000024 00000024 00000024 00000024 00000025 00000025 00000024 00000023 00000023 00000023 00000024 00000024 00000024 00000025 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
dram_vref_reg_value 0x 00000016
2D training succeed
auto size-- 65535DDR cs0 size: 2048MB
DDR cs1 size: 2048MB
DMC_DDR_CTRL: 00e00024DDR size: 3928MB
cs0 DataBus test pass
cs1 DataBus test pass
cs0 AddrBus test pass
cs1 AddrBus test pass
non-sec scramble use zero key
ddr scramble enabled
100bdlr_step_size ps== 403
result report
boot times 0Enable ddr reg access
00000000
emmc switch 3 ok
Authentication key not yet programmed
get rpmb counter error 0x00000007
00000000
emmc switch 0 ok
Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
Load BL3X from eMMC, src: 0x00078200, des: 0x01768000, size: 0x000ce800, part: 0
0.0;M3 CHK:0;cm4_sp_mode 0
MVN_1=0x00000000
MVN_2=0x00000000
[Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
OPS=0x10
ring efuse init
chipver efuse init
29 0b 10 00 01 16 21 00 00 13 31 34 32 58 33 50
[0.018961 Inits done]
secure task start!
high task start!
low task start!
run into bl31
NOTICE: BL31: v1.3(release):4fc40b1
NOTICE: BL31: Built : 15:58:17, May 22 2019
NOTICE: BL31: G12A normal boot!
NOTICE: BL31: BL33 decompress pass
ERROR: Error initializing runtime service opteed_fast
U-Boot 2015.01 (Apr 25 2023 - 08:45:03)
DRAM: 3.8 GiB
Relocation Offset is: d6e42000
spi_post_bind(spifc): req_seq = 0
register usb cfg[0][1] = 00000000d7f39750
aml_i2c_init_port init regs for 0
[aml_i2c_xfer] error ret = -110 i2c master b current slave addr is 0x18
i2c_read: i2c transfer failed