S912 L1 and L2 cache size

The S912 documentation does not mention the size of caches. According to diagram p.14 of the S912 datasheet, each CPU cluster seems to have a dedicated L2 cache, but no size are given. In comparison, s905 has a 512kB cache
Anyone knows about it ?

Using the cache discovery procedure (reading CCSIDR register), it seems S912 has one dedicated L2 unified cache for each CPU cluster of 256KB, meaning 512KB total. It may explain why single thread application may have significant lower performance on s912 than on S905. Any confirmation from Amlogic?

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