Mainline U-Boot sometimes fail with unable to select a mode

VIM3
1

Hello

I have a vim3 with m2x extension powered by POE booted from spi.
Normally it works ok.
But sometimes after a complete power disconnect (No matter if its powered from POE or USB-C).
U-Boot can’t read the boot partition.

After next power disconnect it works again.

U-Boot 2020.04 (Sep 10 2020 - 14:15:14 +0800) khadas-vim3

Model: Khadas VIM3
SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)

Here is the log:
If its not working:
Device 0: unknown device
Card did not respond to voltage select!
Card did not respond to voltage select!
unable to select a mode

If it working:
Device 0: unknown device
Card did not respond to voltage select!
Card did not respond to voltage select!
switch to partitions #0, OK
mmc2(part 0) is current device
Scanning mmc 2:1…
Found U-Boot script /boot.ini
9268 bytes read in 2 ms (4.4 MiB/s)

Script run a:08000000 l:9249 c:0

Starting boot.ini…

Could you give me a hint to solve the problem?

Thanks.

Best regards,
Andreas

Here is the complete log, if it’s not working

G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
bl2_stage_init 0x01
bl2_stage_init 0x81
hw id: 0x0000 - pwm id 0x01
bl2_stage_init 0xc1
bl2_stage_init 0x02

L0:00000000
L1:20000703
L2:00008067
L3:14000000
B2:00402000
B1:e0f83180

TE: 58159

BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz

Board ID = 8
Set A53 clk to 24M
Set A73 clk to 24M
Set clk81 to 24M
A53 clk: 1200 MHz
A73 clk: 1200 MHz
CLK81: 166.6M
smccc: 00012ab5
DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
board id: 8
Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
fw parse done
Load ddrfw from SPI, src: 0x00060000, des: 0xfffd0000, size: 0x0000c000, part: 0
Load ddrfw from SPI, src: 0x00038000, des: 0xfffd0000, size: 0x00004000, part: 0
PIEI prepare done
fastboot data load
fastboot data verify
verify result: 266
Cfg max: 4, cur: 1. Board id: 255. Force loop cfg
LPDDR4 probe
ddr clk to 1608MHz
Load ddrfw from SPI, src: 0x0003c000, des: 0xfffd0000, size: 0x0000c000, part: 0

dmc_version 0001
Check phy result
INFO : End of CA training
INFO : End of initialization
INFO : Training has run successfully!
Check phy result
INFO : End of initialization
INFO : End of read enable training
INFO : End of fine write leveling
INFO : End of Write leveling coarse delay
INFO : Training has run successfully!
Check phy result
INFO : End of initialization
INFO : End of read dq deskew training
INFO : End of MPR read delay center optimization
INFO : End of write delay center optimization
INFO : End of read delay center optimization
INFO : End of max read latency training
INFO : Training has run successfully!
1D training succeed
Load ddrfw from SPI, src: 0x00048000, des: 0xfffd0000, size: 0x0000c000, part: 0
Check phy result
INFO : End of initialization
INFO : End of 2D read delay Voltage center optimization
INFO : End of 2D read delay Voltage center optimization
INFO : End of 2D write delay Voltage center optimization
INFO : End of 2D write delay Voltage center optimization
INFO : Training has run successfully!

channel==0
RxClkDly_Margin_A0==87 ps 9
TxDqDly_Margin_A0==106 ps 11
RxClkDly_Margin_A1==77 ps 8
TxDqDly_Margin_A1==106 ps 11
TrainedVREFDQ_A0==26
TrainedVREFDQ_A1==27
VrefDac_Margin_A0==28
DeviceVref_Margin_A0==26
VrefDac_Margin_A1==30
DeviceVref_Margin_A1==27

channel==1
RxClkDly_Margin_A0==97 ps 10
TxDqDly_Margin_A0==106 ps 11
RxClkDly_Margin_A1==87 ps 9
TxDqDly_Margin_A1==106 ps 11
TrainedVREFDQ_A0==25
TrainedVREFDQ_A1==25
VrefDac_Margin_A0==26
DeviceVref_Margin_A0==24
VrefDac_Margin_A1==27
DeviceVref_Margin_A1==25

dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004

soc_vref_reg_value 0x 00000028 00000028 00000028 00000026 00000028 00000027 00000027 00000027 00000026 00000026 00000025 00000027 00000026 00000027 00000025 00000026 00000028 00000028 00000028 00000029 00000025 00000026 00000025 00000026 00000027 00000027 00000026 00000027 00000027 00000028 00000027 00000027 dram_vref_reg_value 0x 00000013
2D training succeed
aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
auto size-- 65535DDR cs0 size: 2048MB
DDR cs1 size: 2048MB
DMC_DDR_CTRL: 00e00024DDR size: 3928MB
cs0 DataBus test pass
cs1 DataBus test pass
cs0 AddrBus test pass
cs1 AddrBus test pass

100bdlr_step_size ps== 450
result report
boot times 0Enable ddr reg access
Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
Load BL3X from SPI, src: 0x00078000, des: 0x01768000, size: 0x000a0000, part: 0
0.0;M3 CHK:0;cm4_sp_mode 0
MVN_1=0x00000000
MVN_2=0x00000000
[Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
OPS=0x10
ring efuse init
chipver efuse init
29 0b 10 00 01 16 23 00 00 0d 35 37 4d 4d 4e 50
[0.018961 Inits done]
secure task start!
high task start!
low task start!
run into bl31
NOTICE: BL31: v1.3(release):4fc40b1
NOTICE: BL31: Built : 15:58:17, May 22 2019
NOTICE: BL31: G12A normal boot!
NOTICE: BL31: BL33 decompress pass
ERROR: Error initializing runtime service opteed_fast

U-Boot 2020.04 (Sep 10 2020 - 14:15:14 +0800) khadas-vim3

Model: Khadas VIM3
SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
DRAM: 3.8 GiB
MMC: sd@ffe03000: 0, sd@ffe05000: 1, mmc@ffe07000: 2
Loading Environment from FAT… detect… booted from spi - ignored…
In: serial
Out: serial
Err: serial
[i] serial eth mac 8E:BB:1F:50:78:7D
fusb302_init: Device ID: 0x91
Net: eth0: ethernet@ff3f0000
SF: Detected w25q128fw with page size 256 Bytes, erase size 4 KiB, total 16 MiB
device 0 offset 0x170000, size 0x10000
SF: 65536 bytes @ 0x170000 Read: OK
Error: Bad gzipped data
There is no valid bmp file at the given address
starting USB…
Bus usb@ff500000: Register 3000140 NbrPorts 3
Starting the controller
USB XHCI 1.10
scanning bus usb@ff500000 for devices… 3 USB Device(s) found
scanning usb for storage devices… 0 Storage Device(s) found
Setting bus to 0
Hit SPACE in 1 seconds to stop autobootSF: Detected w25q128fw with page size 256 Bytes, erase size 4 KiB, total 16 MiB
device 0 offset 0x160000, size 0x8000
SF: 32768 bytes @ 0x160000 Read: OK
** Script wrong header **

Device 0: unknown device
Card did not respond to voltage select!
Card did not respond to voltage select!
unable to select a mode
Speed: 1000, full duplex
BOOTP broadcast 1
*** Unhandled DHCP Option in OFFER/ACK: 46
*** Unhandled DHCP Option in OFFER/ACK: 46
DHCP client bound to address 10.10.10.82 (6 ms)
Using ethernet@ff3f0000 device
TFTP from server 10.10.10.1; our IP address is 10.10.10.82
Filename ‘boot.scr.uimg’.

And here ist the log if everything is correct

G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
bl2_stage_init 0x01
bl2_stage_init 0x81
hw id: 0x0000 - pwm id 0x01
bl2_stage_init 0xc1
bl2_stage_init 0x02

L0:00000000
L1:20000703
L2:00008067
L3:14000000
B2:00402000
B1:e0f83180

TE: 58168

BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz

Board ID = 8
Set A53 clk to 24M
Set A73 clk to 24M
Set clk81 to 24M
A53 clk: 1200 MHz
A73 clk: 1200 MHz
CLK81: 166.6M
smccc: 00012abe
DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
board id: 8
Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
fw parse done
Load ddrfw from SPI, src: 0x00060000, des: 0xfffd0000, size: 0x0000c000, part: 0
Load ddrfw from SPI, src: 0x00038000, des: 0xfffd0000, size: 0x00004000, part: 0
PIEI prepare done
fastboot data load
fastboot data verify
verify result: 266
Cfg max: 4, cur: 1. Board id: 255. Force loop cfg
LPDDR4 probe
ddr clk to 1608MHz
Load ddrfw from SPI, src: 0x0003c000, des: 0xfffd0000, size: 0x0000c000, part: 0

dmc_version 0001
Check phy result
INFO : End of CA training
INFO : End of initialization
INFO : Training has run successfully!
Check phy result
INFO : End of initialization
INFO : End of read enable training
INFO : End of fine write leveling
INFO : End of Write leveling coarse delay
INFO : Training has run successfully!
Check phy result
INFO : End of initialization
INFO : End of read dq deskew training
INFO : End of MPR read delay center optimization
INFO : End of write delay center optimization
INFO : End of read delay center optimization
INFO : End of max read latency training
INFO : Training has run successfully!
1D training succeed
Load ddrfw from SPI, src: 0x00048000, des: 0xfffd0000, size: 0x0000c000, part: 0
Check phy result
INFO : End of initialization
INFO : End of 2D read delay Voltage center optimization
INFO : End of 2D read delay Voltage center optimization
INFO : End of 2D write delay Voltage center optimization
INFO : End of 2D write delay Voltage center optimization
INFO : Training has run successfully!

channel==0
RxClkDly_Margin_A0==87 ps 9
TxDqDly_Margin_A0==106 ps 11
RxClkDly_Margin_A1==77 ps 8
TxDqDly_Margin_A1==106 ps 11
TrainedVREFDQ_A0==26
TrainedVREFDQ_A1==27
VrefDac_Margin_A0==27
DeviceVref_Margin_A0==26
VrefDac_Margin_A1==30
DeviceVref_Margin_A1==27

channel==1
RxClkDly_Margin_A0==97 ps 10
TxDqDly_Margin_A0==106 ps 11
RxClkDly_Margin_A1==97 ps 10
TxDqDly_Margin_A1==116 ps 12
TrainedVREFDQ_A0==24
TrainedVREFDQ_A1==24
VrefDac_Margin_A0==26
DeviceVref_Margin_A0==24
VrefDac_Margin_A1==26
DeviceVref_Margin_A1==24

dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004

soc_vref_reg_value 0x 00000028 00000028 00000028 00000026 00000028 00000027 00000027 00000027 00000026 00000026 00000025 00000027 00000026 00000027 00000026 00000026 00000028 00000028 00000028 00000028 00000024 00000026 00000025 00000026 00000028 00000027 00000025 00000027 00000027 00000027 00000027 00000027 dram_vref_reg_value 0x 00000013
2D training succeed
aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
auto size-- 65535DDR cs0 size: 2048MB
DDR cs1 size: 2048MB
DMC_DDR_CTRL: 00e00024DDR size: 3928MB
cs0 DataBus test pass
cs1 DataBus test pass
cs0 AddrBus test pass
cs1 AddrBus test pass

100bdlr_step_size ps== 450
result report
boot times 0Enable ddr reg access
Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
Load BL3X from SPI, src: 0x00078000, des: 0x01768000, size: 0x000a0000, part: 0
0.0;M3 CHK:0;cm4_sp_mode 0
MVN_1=0x00000000
MVN_2=0x00000000
[Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
OPS=0x10
ring efuse init
chipver efuse init
29 0b 10 00 01 16 23 00 00 0d 35 37 4d 4d 4e 50
[0.018961 Inits done]
secure task start!
high task start!
low task start!
run into bl31
NOTICE: BL31: v1.3(release):4fc40b1
NOTICE: BL31: Built : 15:58:17, May 22 2019
NOTICE: BL31: G12A normal boot!
NOTICE: BL31: BL33 decompress pass
ERROR: Error initializing runtime service opteed_fast

U-Boot 2020.04 (Sep 10 2020 - 14:15:14 +0800) khadas-vim3

Model: Khadas VIM3
SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
DRAM: 3.8 GiB
MMC: sd@ffe03000: 0, sd@ffe05000: 1, mmc@ffe07000: 2
Loading Environment from FAT… detect… booted from spi - ignored…
In: serial
Out: serial
Err: serial
[i] serial eth mac 8E:BB:1F:50:78:7D
fusb302_init: Device ID: 0x91
Net: eth0: ethernet@ff3f0000
SF: Detected w25q128fw with page size 256 Bytes, erase size 4 KiB, total 16 MiB
device 0 offset 0x170000, size 0x10000
SF: 65536 bytes @ 0x170000 Read: OK
Error: Bad gzipped data
There is no valid bmp file at the given address
starting USB…
Bus usb@ff500000: Register 3000140 NbrPorts 3
Starting the controller
USB XHCI 1.10
scanning bus usb@ff500000 for devices… 3 USB Device(s) found
scanning usb for storage devices… 0 Storage Device(s) found
Setting bus to 0
Hit SPACE in 1 seconds to stop autobootSF: Detected w25q128fw with page size 256 Bytes, erase size 4 KiB, total 16 MiB
device 0 offset 0x160000, size 0x8000
SF: 32768 bytes @ 0x160000 Read: OK
** Script wrong header **

Device 0: unknown device
Card did not respond to voltage select!
Card did not respond to voltage select!
switch to partitions #0, OK
mmc2(part 0) is current device
Scanning mmc 2:1…
Found U-Boot script /boot.ini
9268 bytes read in 2 ms (4.4 MiB/s)

Script run a:08000000 l:9249 c:0

Starting boot.ini…
Setting bus to 0
saradc: 0x0, hw_ver: 0x32 (VIM3.V12)
uboot type: mainline
Scanning mmc 0:1…
Card did not respond to voltage select!
Scanning mmc 0:5…
Card did not respond to voltage select!
Scanning mmc 1:1…
Card did not respond to voltage select!
Scanning mmc 1:5…
Card did not respond to voltage select!
Scanning mmc 2:1…
8307988 bytes read in 348 ms (22.8 MiB/s)
21067784 bytes read in 881 ms (22.8 MiB/s)
51356 bytes read in 3 ms (16.3 MiB/s)
3736 bytes read in 1 ms (3.6 MiB/s)
Import env.txt
Set default mac address to ethaddr: 8e:bb:1f:50:78:7d!
Booting mainline kernel…

2

hello & tnx for report
i will check your problem soon !
plz check last our build https://dl.khadas.com/Firmware/uboot/mainline/
UPDATED: looks like it it last already :wink: OK

3

Hello hyphop
Thanks for your reply.

About the previous problem, please have a look at this post from me.

I have change the bootmode from spi to emmc and burned the bootloader https://dl.khadas.com/Firmware/uboot/main-line/VIM3.uboot-mainline.emmc.aml.img

And now uboot loads from emmc and the rootfs loads from emmc.
And it works every time. Thats ok for me.

I have an other question about the sources.
The build Files (u-boot) from dl.khadas.com - Index of /firmware/uboot/mainline/ comes from which sources?
GitHub - hyphop/khadas-uboot: khadas uboot
or
GitHub - khadas/khadas-uboot: khadas-uboot
or from
GitHub - khadas/fenix: One-stop script set to build Ubuntu/Debian images

And the second question about u-boot is
Will it be possible in the near future to detect an nvme disc in u-boot?
Should it be possible by enable PCIE mode in the dts file and enable nvme in the defconfig file?

Thanks in advice for your answer.
Regards, Andreas

4

GitHub - khadas/khadas-uboot: khadas-uboot - this one > dl.khadas.com - Index of /firmware/uboot/mainline/

And now uboot loads from emmc and the rootfs loads from emmc.

this uboot can start rootfs from usb | sd | emmc | …

Will it be possible in the near future to detect an nvme disc in u-boot?

mainline uboot for Amlogic still dont have NVME PCIE support

Should it be possible by enable PCIE mode in the dts file and enable nvme in the defconfig file?

sure but its will be work already in kernel stage not in uboot

also possible activate in uboot script as https://github.com/krescue/khadas-rescue-sdk/blob/master/files/rescue.cmd#L202
or same in fenix fenix/config/bootscripts/aml_boot.ini at master · khadas/fenix · GitHub