G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:0;READ:0;CHK:1F;READ:0;CHK:1F;READ:0;CHK:1F;SD?:0;SD:0;READ:0;0.▒!,K▒▒х▒▒}▒▒▒с0x01
bl2_stage_init 0x81
hw id: 0x0001 - pwm id 0x00
bl2_stage_init 0xc0
bl2_stage_init 0x02
no sdio debug board detected
L0:00000000
L1:20000703
L2:00008067
L3:14000000
B2:00402000
B1:e0f83180
TE: 337884
BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
Board ID = 1
Set A53 clk to 24M
Set A73 clk to 24M
Set clk81 to 24M
A53 clk: 1200 MHz
A73 clk: 1200 MHz
CLK81: 166.6M
smccc: 00056fb9
DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
board id: 1
Load FIP HDR from SD, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0
fw parse done
Load ddrfw from SD, src: 0x00060200, des: 0xfffd0000, size: 0x0000c000, part: 0
Load ddrfw from SD, src: 0x00038200, des: 0xfffd0000, size: 0x00004000, part: 0
PIEI prepare done
fastboot data load
fastboot data verify
verify result: 266
Cfg max: 4, cur: 1. Board id: 255. Force loop cfg
LPDDR4 probe
ddr clk to 1608MHz
Load ddrfw from SD, src: 0x0003c200, des: 0xfffd0000, size: 0x0000c000, part: 0
dmc_version 0001
Check phy result
INFO : ERROR : Training has failed!
1D training failed
Cfg max: 4, cur: 2. Board id: 255. Force loop cfg
LPDDR4 probe
ddr clk to 1608MHz
Load ddrfw from SD, src: 0x0003c200, des: 0xfffd0000, size: 0x0000c000, part: 0
dmc_version 0001
Check phy result
INFO : End of CA training
INFO : End of initialization
INFO : Training has run successfully!
Check phy result
INFO : End of initialization
INFO : End of read enable training
INFO : End of fine write leveling
INFO : End of Write leveling coarse delay
INFO : Training has run successfully!
Check phy result
INFO : End of initialization
INFO : End of read dq deskew training
INFO : End of MPR read delay center optimization
INFO : End of write delay center optimization
INFO : End of read delay center optimization
INFO : End of max read latency training
INFO : Training has run successfully!
1D training succeed
Load ddrfw from SD, src: 0x00048200, des: 0xfffd0000, size: 0x0000c000, part: 0
Check phy result
INFO : End of initialization
INFO : End of 2D read delay Voltage center optimization
INFO : End of 2D read delay Voltage center optimization
INFO : End of 2D write delay Voltage center optimization
INFO : End of 2D write delay Voltage center optimization
INFO : Training has run successfully!
channel==0
RxClkDly_Margin_A0==97 ps 10
TxDqDly_Margin_A0==106 ps 11
RxClkDly_Margin_A1==0 ps 0
TxDqDly_Margin_A1==0 ps 0
TrainedVREFDQ_A0==25
TrainedVREFDQ_A1==0
VrefDac_Margin_A0==25
DeviceVref_Margin_A0==25
VrefDac_Margin_A1==0
DeviceVref_Margin_A1==0
channel==1
RxClkDly_Margin_A0==106 ps 11
TxDqDly_Margin_A0==97 ps 10
RxClkDly_Margin_A1==0 ps 0
TxDqDly_Margin_A1==0 ps 0
TrainedVREFDQ_A0==26
TrainedVREFDQ_A1==0
VrefDac_Margin_A0==24
DeviceVref_Margin_A0==26
VrefDac_Margin_A1==0
DeviceVref_Margin_A1==0
dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
soc_vref_reg_value 0x 00000026 00000026 00000026 00000026 00000026 00000027 00000028 00000025 0000002a 00000026 00000025 00000023 00000026 00000026 00000027 00000027 00000026 00000025 00000023 00000023 00000025 00000024 00000025 00000022 00000022 00000024 00000024 00000027 00000023 00000025 00000023 00000024 dram_vref_reg_value 0x 00000012
2D training succeed
aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
auto size-- 65535DDR cs0 size: 2048MB
DDR cs1 size: 0MB
DMC_DDR_CTRL: 00c0002cDDR size: 2048MB
cs0 DataBus test pass
cs0 AddrBus test pass
100bdlr_step_size ps== 485
result report
boot times 0Enable ddr reg access
Load FIP HDR from SD, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
Load BL3X from SD, src: 0x00078200, des: 0x01768000, size: 0x000a0000, part: 0
0.0;M3 CHK:0;cm4_sp_mode 0
MVN_1=0x00000000
MVN_2=0x00000000
[Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
OPS=0x10
ring efuse init
chipver efuse init
29 0b 10 00 01 16 1b 00 00 18 36 36 52 39 53 50
[0.018960 Inits done]
secure task start!
high task start!
low task start!
run into bl31
NOTICE: BL31: v1.3(release):4fc40b1
NOTICE: BL31: Built : 15:58:17, May 22 2019
NOTICE: BL31: G12A normal boot!
NOTICE: BL31: BL33 decompress pass
ERROR: Error initializing runtime service opteed_fast
U-Boot 2020.04 (May 30 2020 - 15:53:24 +0800) khadas-vim3
Model: Khadas VIM3
SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
DRAM: 2 GiB
MMC: sd@ffe03000: 0, sd@ffe05000: 1, mmc@ffe07000: 2
Loading Environment from FAT… unable to select a mode
detect… booted from sd…
OK
In: serial
Out: serial
Err: serial
Net: eth0: ethernet@ff3f0000
unable to select a mode
750054 bytes read in 41 ms (17.4 MiB/s)
starting USB…
Bus usb@ff500000: probe failed, error -110
No working controllers found
Setting bus to 0
Hit any key to stop autoboot: 0
unrecognized JEDEC id bytes: ff, ff, ff
Failed to initialize SPI flash at 0:0 (error -2)
starting USB…
Bus usb@ff500000: probe failed, error -110
No working controllers found
USB is stopped. Please issue ‘usb start’ first.
Card did not respond to voltage select!
switch to partitions #0, OK
mmc1 is current device
Scanning mmc 1:1…
Found U-Boot script /boot.ini
8282 bytes read in 4 ms (2 MiB/s)
Script run a:08000000 l:8263 c:0
Starting boot.ini…
Setting bus to 0
saradc: 0x0, hw_ver: 0x32 (VIM3.V12)
uboot type: mainline
Scanning mmc 0:1…
Card did not respond to voltage select!
Scanning mmc 0:5…
Card did not respond to voltage select!
Scanning mmc 1:1…
11971430 bytes read in 525 ms (21.7 MiB/s)
20969480 bytes read in 918 ms (21.8 MiB/s)
50997 bytes read in 5 ms (9.7 MiB/s)
2792 bytes read in 2 ms (1.3 MiB/s)
Import env.txt
Found custom ethmac: 12:d6:12:32:9a:6d, overwrite eth_mac!
Booting mainline kernel…
libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND
Setting bus to 0
port mode is usb3.0
Loading init Ramdisk from Legacy Image at 13000000 …
Image Name: uInitrd
Image Type: AArch64 Linux RAMDisk Image (gzip compressed)
Data Size: 11971366 Bytes = 11.4 MiB
Load Address: 00000000
Entry Point: 00000000
Verifying Checksum … OK
Flattened Device Tree blob at 01000000
Booting using the fdt blob at 0x1000000
Loading Ramdisk to 7b3a2000, end 7bf0cb26 … OK
Loading Device Tree to 000000007b32d000, end 000000007b3a1fff … OK
Starting kernel …
G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:0;READ:0;CHK:1F;READ:0;CHK:1F;READ:0;CHK:1F;SD?:0;SD:0;READ:0;0.
bl2_stage_init 0x01
bl2_stage_init 0x81
hw id: 0x0001 - pwm id 0x00
bl2_stage_init 0xc0
bl2_stage_init 0x02
no sdio debug board detected
L0:00000000
L1:20000703
L2:00008067
L3:14000000
B2:00402000
B1:e0f83180
TE: 337893
BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
Board ID = 1
Set A53 clk to 24M
Set A73 clk to 24M
Set clk81 to 24M
A53 clk: 1200 MHz
A73 clk: 1200 MHz
CLK81: 166.6M
smccc: 00056fc2
DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
board id: 1
Load FIP HDR from SD, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0
fw parse done
Load ddrfw from SD, src: 0x00060200, des: 0xfffd0000, size: 0x0000c000, part: 0
Load ddrfw from SD, src: 0x00038200, des: 0xfffd0000, size: 0x00004000, part: 0
PIEI prepare done
fastboot data load
fastboot data verify
verify result: 266
Cfg max: 4, cur: 1. Board id: 255. Force loop cfg
LPDDR4 probe
ddr clk to 1608MHz
Load ddrfw from SD, src: 0x0003c200, des: 0xfffd0000, size: 0x0000c000, part: 0
dmc_version 0001
Check phy result
INFO : ERROR : Training has failed!
1D training failed
Cfg max: 4, cur: 2. Board id: 255. Force loop cfg
LPDDR4 probe
ddr clk to 1608MHz
Load ddrfw from SD, src: 0x0003c200, des: 0xfffd0000, size: 0x0000c000, part: 0
dmc_version 0001
Check phy result
INFO : End of CA training
INFO : End of initialization
INFO : Training has run successfully!
Check phy result
INFO : End of initialization
INFO : End of read enable training
INFO : End of fine write leveling
INFO : End of Write leveling coarse delay
INFO : Training has run successfully!
Check phy result
INFO : End of initialization
INFO : End of read dq deskew training
INFO : End of MPR read delay center optimization
INFO : End of write delay center optimization
INFO : End of read delay center optimization
INFO : End of max read latency training
INFO : Training has run successfully!
1D training succeed
Load ddrfw from SD, src: 0x00048200, des: 0xfffd0000, size: 0x0000c000, part: 0
Check phy result
INFO : End of initialization
INFO : End of 2D read delay Voltage center optimization
INFO : End of 2D read delay Voltage center optimization
INFO : End of 2D write delay Voltage center optimization
INFO : End of 2D write delay Voltage center optimization
INFO : Training has run successfully!
channel==0
RxClkDly_Margin_A0==97 ps 10
TxDqDly_Margin_A0==97 ps 10
RxClkDly_Margin_A1==0 ps 0
TxDqDly_Margin_A1==0 ps 0
TrainedVREFDQ_A0==27
TrainedVREFDQ_A1==0
VrefDac_Margin_A0==25
DeviceVref_Margin_A0==26
VrefDac_Margin_A1==0
DeviceVref_Margin_A1==0
channel==1
RxClkDly_Margin_A0==97 ps 10
TxDqDly_Margin_A0==97 ps 10
RxClkDly_Margin_A1==0 ps 0
TxDqDly_Margin_A1==0 ps 0
TrainedVREFDQ_A0==26
TrainedVREFDQ_A1==0
VrefDac_Margin_A0==24
DeviceVref_Margin_A0==25
VrefDac_Margin_A1==0
DeviceVref_Margin_A1==0
dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
soc_vref_reg_value 0x 00000026 00000026 00000026 00000026 00000026 00000027 00000028 00000026 00000029 00000026 00000025 00000023 00000026 00000026 00000027 00000027 00000026 00000025 00000023 00000023 00000025 00000024 00000024 00000022 00000022 00000024 00000024 00000027 00000023 00000025 00000023 00000024 dram_vref_reg_value 0x 00000012
2D training succeed
aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
auto size-- 65535DDR cs0 size: 2048MB
DDR cs1 size: 0MB
DMC_DDR_CTRL: 00c0002cDDR size: 2048MB
cs0 DataBus test pass
cs0 AddrBus test pass
100bdlr_step_size ps== 485
result report
boot times 0Enable ddr reg access
Load FIP HDR from SD, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
Load BL3X from SD, src: 0x00078200, des: 0x01768000, size: 0x000a0000, part: 0
0.0;M3 CHK:0;cm4_sp_mode 0
MVN_1=0x00000000
MVN_2=0x00000000
[Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
OPS=0x10
ring efuse init
chipver efuse init
29 0b 10 00 01 16 1b 00 00 18 36 36 52 39 53 50
[0.018961 Inits done]
secure task start!
high task start!
low task start!
run into bl31
NOTICE: BL31: v1.3(release):4fc40b1
NOTICE: BL31: Built : 15:58:17, May 22 2019
NOTICE: BL31: G12A normal boot!
NOTICE: BL31: BL33 decompress pass
ERROR: Error initializing runtime service opteed_fast
U-Boot 2020.04 (May 30 2020 - 15:53:24 +0800) khadas-vim3
Model: Khadas VIM3
SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
DRAM: 2 GiB
MMC: sd@ffe03000: 0, sd@ffe05000: 1, mmc@ffe07000: 2
Loading Environment from FAT… unable to select a mode
detect… booted from sd…
OK
In: serial
Out: serial
Err: serial
Net: eth0: ethernet@ff3f0000
unable to select a mode
750054 bytes read in 42 ms (17 MiB/s)
starting USB…
Bus usb@ff500000: probe failed, error -110
No working controllers found
Setting bus to 0
Hit any key to stop autoboot: 0
unrecognized JEDEC id bytes: ff, ff, ff
Failed to initialize SPI flash at 0:0 (error -2)
starting USB…
Bus usb@ff500000: probe failed, error -110
No working controllers found
USB is stopped. Please issue ‘usb start’ first.
Card did not respond to voltage select!
switch to partitions #0, OK
mmc1 is current device
Scanning mmc 1:1…
Found U-Boot script /boot.ini
8282 bytes read in 4 ms (2 MiB/s)
Script run a:08000000 l:8263 c:0
Starting boot.ini…
Setting bus to 0
saradc: 0x0, hw_ver: 0x32 (VIM3.V12)
uboot type: mainline
Scanning mmc 0:1…
Card did not respond to voltage select!
Scanning mmc 0:5…
Card did not respond to voltage select!
Scanning mmc 1:1…
11971430 bytes read in 525 ms (21.7 MiB/s)
20969480 bytes read in 918 ms (21.8 MiB/s)
50997 bytes read in 5 ms (9.7 MiB/s)
2792 bytes read in 2 ms (1.3 MiB/s)
Import env.txt
Found custom ethmac: 12:d6:12:32:9a:6d, overwrite eth_mac!
Booting mainline kernel…
libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND
Setting bus to 0
port mode is usb3.0
Loading init Ramdisk from Legacy Image at 13000000 …
Image Name: uInitrd
Image Type: AArch64 Linux RAMDisk Image (gzip compressed)
Data Size: 11971366 Bytes = 11.4 MiB
Load Address: 00000000
Entry Point: 00000000
Verifying Checksum … OK
Flattened Device Tree blob at 01000000
Booting using the fdt blob at 0x1000000
Loading Ramdisk to 7b3a2000, end 7bf0cb26 … OK
Loading Device Tree to 000000007b32d000, end 000000007b3a1fff … OK
Starting kernel …