关于vim3l uboot代码下载和编译问题

你好 我想询问下vim3l uboot代码下载和编译问题
首先,我在https://github.com/khadas/u-boot/tree/khadas-vims-v2015.01/ 下载代码的zip包,然后解压缩 但是我发现config里 没有kvim31_defconfig 这个文件。请问分支选择是否正确?

其次,我使用的虚拟机是16.04 ,已经安装了aarch64-linux-gnu-gcc 版本号是5.4 我是否还需要重新安装GCC。

没事Android还是linux? 这个分支是linux 的,defconfig文件在目录:

Android uboot:

Hi 感谢回复,

我使用的是linux的uboot. 我已经找到defconfig文件,关于编译遇到以下问题:
我在uboot目录下执行 export ARCH=arm64 
                                   export CROSS_COMPILE=aarch64-linux-gnu-
                                   make kvim3l_defconfig

以上命令 会报错,报错如下:
  HOSTCC  scripts/basic/fixdep

/bin/sh: 1: cc: not found
scripts/Makefile.host:91: recipe for target ‘scripts/basic/fixdep’ failed
make[2]: *** [scripts/basic/fixdep] Error 127
/home/lyf/Downloads/lp4/u-boot-khadas-vims-v2015.01/Makefile:395: recipe for target ‘scripts_basic’ failed
make[1]: *** [scripts_basic] Error 2
Makefile:147: recipe for target ‘sub-make’ failed
make: *** [sub-make] Error 2

报错说的很明确,交叉编译器没有安装。

建议参考这个编译uboot。

我的虚拟机上已经安装过ARMV8的GCC 如下:
lyf@ubuntu:~/Downloads/lp4/fenix-master$ aarch64-linux-gnu-gcc -v
Using built-in specs.
COLLECT_GCC=aarch64-linux-gnu-gcc
COLLECT_LTO_WRAPPER=/usr/lib/gcc-cross/aarch64-linux-gnu/5/lto-wrapper
版本号是5.4

但是我这边用fenix make uboot时 会产生错误,错误如下:
Connecting to publishing-ap-linaro-org.s3.amazonaws.com (publishing-ap-linaro-org.s3.amazonaws.com)|0.0.0.0|:443… failed: Connection refused.
config/functions/build-package:76 Error: Cant’t get gcc-linaro-aarch64-linux-gnu sources : https://releases.linaro.org/components/toolchain/binaries/7.3-2018.05/aarch64-linux-gnu/gcc-linaro-7.3.1-2018.05-x86_64_aarch64-linux-gnu.tar.xz
Try later !!

网络问题,试试:

DOWNLOAD_MIRROR=china make

fenix 下 输入 DOWNLOAD_MIRROR=china
make uboot

依然是报错,Connecting to publishing-ap-linaro-org.s3.amazonaws.com (publishing-ap-linaro-org.s3.amazonaws.com)|0.0.0.0|:443… failed: Connection refused.
config/functions/build-package:76 Error: Cant’t get gcc-linaro-aarch64-linux-gnu sources : https://releases.linaro.org/components/toolchain/binaries/7.3-2018.05/aarch64-linux-gnu/gcc-linaro-7.3.1-2018.05-x86_64_aarch64-linux-gnu.tar.xz
Try later !!

和不输入DOWMLOAD_MIRROR=china的错误一致。

似乎还是网络问题,可以试着开vpn试下。

你好 我已经通过vpn更新了UBOOT 并完成编译,目前在调试串口,我按照文档安装了kermit
权限也设置正确,但是reset 板子没有任何log输出,也无法输入
kermit
Connecting to /dev/ttyUSB0, speed 115200
Escape character: Ctrl-\ (ASCII 28, FS): enabled
Type the escape character followed by C to get back,
or followed by ? to see other options.

???
???

         ?
            ?
              ???

??? ?

 ?????????

Communications disconnect (Back at luyanfei-virtual-machine)

C-Kermit 9.0.302 OPEN SOURCE:, 20 Aug 2011, for Linux+SSL+KRB5 (64-bit)
Copyright © 1985, 2011,
Trustees of Columbia University in the City of New York.
Type ? or HELP for help.
(/home/luyanfei/) C-Kermit>

确认下串口连线是否正确吧。

感谢 我们更换了一根串口线 已经可以正常输出LOG了

还有一个问题想请教下: 我已经编译完u-boot.bin 我看板子现在是从emmc启动,如果我烧写u-boot.bin到spl flash 上,是否可以通过设置不同的bootmode 来选择希望从SPL或者EMMC 的uboot来启动呢

我看burning命令里
kvim3#sf erase 0 +$filesize 这个$filesize 是需要写具体的u-boot.bin的文件大小吗?

可以的。

filesize这个变量实在load后自动生成的,表示你load到DDR的文件的大小。你直接这样操作就行。

谢谢,如果我烧录进去一个无法启动的uboot 是否有补救措施 再刷会正常版本?

TST模式重刷固件

谢谢回复,目前在研读Uboot代码和串口输出的打印信息,我看了下vlm3l板子在初始化时有一段LOG我在uboot中没有搜索到,想询问下 这部分代码是否可以看到,LOG如下:
Board ID = 8
Set cpu clk to 24M
Set clk81 to 24M
Use GP1_pll as DSU clk.
DSU clk: 1200 Mhz
CPU clk: 1200 MHz
Set clk81 to 166.6M
eMMC boot @ 0
sw8 s
DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Jul 31 2019 19:17:43
board id: 8
Load FIP HDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0
fw parse done
Load ddrfw from eMMC, src: 0x00060200, des: 0xfffd0000, size: 0x0000c000, part: 0
Load ddrfw from eMMC, src: 0x00038200, des: 0xfffd0000, size: 0x00004000, part: 0
PIEI prepare done
fastboot data load
00000000
emmc switch 1 ok
ddr saved addr:00016000
Load ddr parameter from eMMC, src: 0x02c00000, des: 0xfffd0000, size: 0x00001000, part: 0
00000000
emmc switch 0 ok
fastboot data verify
verify result: 265
Cfg max: 4, cur: 1. Board id: 255. Force loop cfg
LPDDR4 probe
ddr clk to 1608MHz
Load ddrfw from eMMC, src: 0x0003c200, des: 0xfffd0000, size: 0x0000c000, part: 0

dmc_version 0001
Check phy result
INFO : ERROR : Training has failed!
1D training failed
Cfg max: 4, cur: 2. Board id: 255. Force loop cfg
LPDDR4 probe
ddr clk to 1608MHz
Load ddrfw from eMMC, src: 0x0003c200, des: 0xfffd0000, size: 0x0000c000, part: 0

dmc_version 0001
Check phy result
INFO : End of CA training
INFO : End of initialization
INFO : Training has run successfully!
Check phy result
INFO : End of initialization
INFO : End of read enable training
INFO : End of fine write leveling
INFO : End of Write leveling coarse delay
INFO : Training has run successfully!
Check phy result
INFO : End of initialization
INFO : End of read dq deskew training
INFO : End of MPR read delay center optimization
INFO : End of write delay center optimization
INFO : End of read delay center optimization
INFO : End of max read latency training
INFO : Training has run successfully!
1D training succeed
Load ddrfw from eMMC, src: 0x00048200, des: 0xfffd0000, size: 0x0000c000, part: 0
Check phy result
INFO : End of initialization
INFO : End of 2D read delay Voltage center optimization
INFO : End of 2D read delay Voltage center optimization
INFO : End of 2D write delay Voltage center optimization
INFO : End of 2D write delay Voltage center optimization
INFO : Training has run successfully!

channel==0
RxClkDly_Margin_A0==87 ps 9
TxDqDly_Margin_A0==106 ps 11
RxClkDly_Margin_A1==0 ps 0
TxDqDly_Margin_A1==0 ps 0
TrainedVREFDQ_A0==30
TrainedVREFDQ_A1==0
VrefDac_Margin_A0==29
DeviceVref_Margin_A0==30
VrefDac_Margin_A1==0
DeviceVref_Margin_A1==0

channel==1
RxClkDly_Margin_A0==97 ps 10
TxDqDly_Margin_A0==106 ps 11
RxClkDly_Margin_A1==0 ps 0
TxDqDly_Margin_A1==0 ps 0
TrainedVREFDQ_A0==29
TrainedVREFDQ_A1==0
VrefDac_Margin_A0==27
DeviceVref_Margin_A0==29
VrefDac_Margin_A1==0
DeviceVref_Margin_A1==0

dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004

soc_vref_reg_value 0x 00000028 00000027 00000027 00000027 00000027 00000027 00000027 00000026 00000026 00000026 00000025 00000027 00000025 00000026 00000027 00000025 00000025 00000026 00000026 00000027 00000025 00000027 00000025 00000025 00000026 00000027 00000025 00000024 00000027 00000026 00000026 00000026 dram_vref_reg_value 0x 00000014
2D training succeed
aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Jul 31 2019 19:17:53
auto size-- 65535DDR cs0 size: 2048MB
DDR cs1 size: 0MB
DMC_DDR_CTRL: 00c0002cDDR size: 2048MB
cs0 DataBus test pass
cs0 AddrBus test pass

100bdlr_step_size ps== 444
result report
boot times 0Enable ddr reg access
00000000
emmc switch 3 ok
Authentication key not yet programmed
get rpmb counter error 0x00000007
00000000
emmc switch 0 ok
Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
Load BL3X from eMMC, src: 0x00078200, des: 0x01768000, size: 0x000bfa00, part: 0
0.0;M3 CHK:0;cm4_sp_mode 0
MVN_1=0x00000000
MVN_2=0x00000000
[Image: g12a_v1.1.3389-92241b5 2019-07-02 17:22:49 luan.yuan@droid15-sz]
OPS=0x04
ring efuse init
2b 0c 04 00 01 08 09 00 00 05 34 39 39 46 38 50
[0.017310 Inits done]
secure task start!
high task start!
low task start!
run into bl31
NOTICE: BL31: v1.3(release):4fc40b1
NOTICE: BL31: Built : 15:57:33, May 22 2019
NOTICE: BL31: G12A normal boot!
NOTICE: BL31: BL33 decompress pass
ERROR: Error initializing runtime service opteed_fast

请问这部分代码在UBOOT中是否可以看到?

这是uboot之前的bin文件打印的,这部分是不开源的。

如果我们想更改lpddr4相关时序 来做对比测试,请问目前的Uboot代码可以支持吗?

DDR包含几部分的。有一部分是不开源的bin文件,这个你们无法更改。还有一分部是timing,你可以试着改timing文件。

你好 我想问下timing.c中的dram_cs0_size_MB这个成员 0xffff这个值是如何与1024对应的,我将这个值改成0x7fff 重新烧录uboot,为何开发板启动时 检测内存容量变成3.8GB 。没修改之前是2GB

0xffff表示自动检测DDR容量大小。