Hi @Terry do you want me to upload to baidu?
1 Like
I couldn’t update your ROM with v1.2 VIM3. I think you need to update to the new SDK source code V190823
BL2 Built : 19:22:38, Jun 28 2019. g12b ga659aac-dirty - zhiguang.ouyang@droid04-sz
Board ID = 8
Set A53 clk to 24M
Set A73 clk to 24M
Set clk81 to 24M
A53 clk: 1200 MHz
A73 clk: 1200 MHz
CLK81: 166.6M
smccc: 003774bd
DDR driver_vesion: LPDDR4_PHY_V_0_1_15 build time: Jun 28 2019 19:22:33
board id: 8
Cfg max: 3, cur: 1. Board id: 255. Force loop cfg
DATA transfer complete...
fw parse done
DATA transfer complete...
AML DDR FW load done
DATA transfer complete...
PIEI prepare done
LPDDR4 probe
ddr clk to 1608MHz
DATA transfer complete...
dmc_version 0001
Check phy result
INFO : End of CA training
INFO : End of initialization
INFO : Training has run successfully!
Check phy result
INFO : End of initialization
INFO : End of read enable training
INFO : End of fine write leveling
INFO : End of Write leveling coarse delay
INFO : Training has run successfully!
Check phy result
INFO : End of initialization
INFO : End of read dq deskew training
INFO : End of MPR read delay center optimization
INFO : ERROR : Training has failed!
Cfg max: 3, cur: 2. Board id: 255. Force loop cfg
ddr probe id done
DATA transfer complete...
fw parse done
DATA transfer complete...
AML DDR FW load done
DATA transfer complete...
PIEI prepare done
LPDDR4 probe
ddr clk to 1608MHz
DATA transfer complete...
dmc_version 0001
Check phy result
INFO : End of CA training
INFO : End of initialization
INFO : Training has run successfully!
Check phy result
INFO : End of initialization
INFO : End of read enable training
INFO : End of fine write leveling
INFO : ERROR : Training has failed!
Cfg max: 3, cur: 3. Board id: 255. Force loop cfg
ddr probe id done
DATA transfer complete...
fw parse done
DATA transfer complete...
AML DDR FW load done
DATA transfer complete...
PIEI prepare done
LPDDR4 probe
ddr clk to 1608MHz
DATA transfer complete...
dmc_version 0001
Check phy result
INFO : End of CA training
INFO : End of initialization
INFO : Training has run successfully!
Check phy result
INFO : End of initialization
INFO : End of read enable training
INFO : End of fine write leveling
INFO : ERROR : Training has failed!
All ddr config failed...
Try next cfg
Exit data request loop...Err0x00000020
1 Like
Hi, superceleron
BTW, If you don’t want to repo sync the new SDK source code. You can only check pick this commit
Apply this patch to let VIM3 V12 DDR to run at 1608MHz.
1 Like
Yes as i suspected uboot changes, thks for confirming it @Terry, im going to merge that change for now, or i m8 checkout the new sdk and start clean.
Still thinking what to do.
3 Likes
Good afternoon, friends! If it’s not a secret, at what frequency does v11 work?
Superceleron, really looking forward to your firmware for v12, thank you very much!
Well i still dint had time to do any work, my build server PSU died so i had to wait to buy another since they are expensive… actually it just arrive today.
3 Likes
Friends, Auto Frame Rate will be implemented?
About that i dont plan on implementing it, i will make a twrp (i already have it working but still some issues to fix) and then you root it and theirs a app in 4pda that will do that for you!
On side note, i just did all changes needed for v1.2 and connect button in wifi, looking good.
It will be based still on old sdk, as it going to take a while for me to port all my changes to new sdk…
But i will need @Terry to try it 1º in a v1.2 to see if it really working on it!
4 Likes
A good idea! thanks for the work!
Well, @Robert just tested it for me in v1.2 and all good, so i will be updating my both builds to support the vim3 hw revision 1.2, it still works on older revision just fine!
3 Likes
Yes, the latest DDR patch suit for both V11(Samsung LPDDR4) and V12(SkHynix LPDDR4).
3 Likes
yes, nice works there 
im still using old sdk, in due time i will port my changes to new sdk and or course make some new PIE FW ( Normal and ATV ) for VIM1 and VIM3
3 Likes
Friends, is it possible to implement the noise reduction function for an image, is it as if turned on by default, or am I mistaken? thank!
That is maybe offtopic, but it was sad to see SkHynix instead of Samsung on my VIM3 Pro 
2 Likes
yes i enable it by default in my build.
Anyway after some thinking im not going to rls the fixed build based on old sdk… do not worth it!
So i decided im going to port all my work to the new sdk and then rls it!
4 Likes
Hi… Just to let you guys know i ported all my changes to the new sdk(and fixed some issues present in new sdk) i should rls the build today!
I gave test builds to @Robert and @RDFTKV just waiting for some feedback!
6 Likes
Wondering why sad on this 
Firstly, all the Samsung LPDDR4 with 200-ball are not available for sourcing at the time we arranged the SMT process. Secondly, I think the SkHynix is one of the top 3 memory vendor in the world.
1 Like
At the peak of Ethereum mining Nvidia had some of their video card models exactly the same just memory had two options: Samsung or SkHynix - although numbers were exactly the same, devices performed much better with Samsung memory…
I think that if some industrial project wants the best of the best DRAM perf, it can order from khadas a special batch of boards that could effectively be used in search of optimal performances. The “ordinary” boards are more aimed at DIYers and makers for prototyping purpose
I guess it runs different frequency.
Actually, it’s same performance on VIM3, and both run at 1608MHz.