Reset loop - white led flashing

Hello all,

While trying to boot a khadas vim3 pro card I am encountering a boot/reset loop.
Since I had a TTL lying around I’ve connected it and it is getting this


reset…

G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:0;READ:0;CHK:1F;READ:0;CHK:1F;READ:0;CHK:1F;SD?:0;SD:0;READ:0;0…!,K???..}???.0x01

bl2_stage_init 0x81

hw id: 0x0000 - pwm id 0x01

bl2_stage_init 0xc1

bl2_stage_init 0x02

no sdio debug board detected

L0:00000000

L1:20000703

L2:00008067

L3:14000000

B2:00402000

B1:e0f83180

TE: 406454

BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz

Board ID = 8

Set A53 clk to 24M

Set A73 clk to 24M

Set clk81 to 24M

A53 clk: 1200 MHz

A73 clk: 1200 MHz

CLK81: 166.6M

smccc: 00067b93

DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01

board id: 8

Load FIP HDR from SD, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0

fw parse done

Load ddrfw from SD, src: 0x00060200, des: 0xfffd0000, size: 0x0000c000, part: 0

Load ddrfw from SD, src: 0x00038200, des: 0xfffd0000, size: 0x00004000, part: 0

PIEI prepare done

fastboot data load

fastboot data verify

verify result: 266

Cfg max: 4, cur: 1. Board id: 255. Force loop cfg

LPDDR4 probe

ddr clk to 1608MHz

Load ddrfw from SD, src: 0x0003c200, des: 0xfffd0000, size: 0x0000c000, part: 0

dmc_version 0001

Check phy result

INFO : End of CA training

INFO : End of initialization

INFO : Training has run successfully!

Check phy result

INFO : End of initialization

INFO : End of read enable training

INFO : End of fine write leveling

INFO : End of Write leveling coarse delay

INFO : Training has run successfully!

Check phy result

INFO : End of initialization

INFO : End of read dq deskew training

INFO : End of MPR read delay center optimization

INFO : End of write delay center optimization

INFO : End of read delay center optimization

INFO : End of max read latency training

INFO : Training has run successfully!

1D training succeed

Load ddrfw from SD, src: 0x00048200, des: 0xfffd0000, size: 0x0000c000, part: 0

Check phy result

INFO : End of initialization

INFO : End of 2D read delay Voltage center optimization

INFO : End of 2D read delay Voltage center optimization

INFO : End of 2D write delay Voltage center optimization

INFO : End of 2D write delay Voltage center optimization

INFO : Training has run successfully!

channel==0

RxClkDly_Margin_A0==87 ps 9

TxDqDly_Margin_A0==97 ps 10

RxClkDly_Margin_A1==58 ps 6

TxDqDly_Margin_A1==106 ps 11

TrainedVREFDQ_A0==28

TrainedVREFDQ_A1==27

VrefDac_Margin_A0==28

DeviceVref_Margin_A0==27

VrefDac_Margin_A1==31

DeviceVref_Margin_A1==27

channel==1

RxClkDly_Margin_A0==106 ps 11

TxDqDly_Margin_A0==106 ps 11

RxClkDly_Margin_A1==97 ps 10

TxDqDly_Margin_A1==106 ps 11

TrainedVREFDQ_A0==25

TrainedVREFDQ_A1==26

VrefDac_Margin_A0==27

DeviceVref_Margin_A0==25

VrefDac_Margin_A1==28

DeviceVref_Margin_A1==25

dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004

soc_vref_reg_value 0x 00000027 00000027 00000028 00000027 00000026 00000024 00000026 00000026 00000028 00000026 00000024 00000025 00000026 00000027 00000025 00000028 00000026 00000027 00000028 00000028 00000027 00000027 00000027 00000027 00000029 00000027 00000029 00000027 0003

2D training succeed

aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19

auto size-- 65535DDR cs0 size: 2048MB

DDR cs1 size: 2048MB

DMC_DDR_CTRL: 00e00024DDR size: 3928MB

cs0 DataBus test pass

cs1 DataBus test pass

cs0 AddrBus test pass

cs1 AddrBus test pass

100bdlr_step_size ps== 388

result report

boot times 0Enable ddr reg access

Load FIP HDR from SD, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0

FIP HDR CHK: 0x00000097 ADDR 0x01700000

reset…

When I am trying to boot from the Android img I am getting this via serial, though no input, I cannot type anything

Welcome to minicom 2.7.1

OPTIONS: I18n
Compiled on May 6 2018, 10:36:56.
Port /dev/ttyUSB0, 12:50:34

Press CTRL-A Z for help on special keys

G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:0;READ:0;CHK:1F;READ:0;CHK:1F;READ:0;CHK:1F;SD?:0;SD:0;READ:0;0…
bl2_stage_init 0x01
bl2_stage_init 0x81
hw id: 0x0000 - pwm id 0x01
bl2_stage_init 0xc1
bl2_stage_init 0x02

no sdio debug board detected
L0:00000000
L1:20000703
L2:00008067
L3:14000000
B2:00402000
B1:e0f83180

TE: 579372

BL2 Built : 16:01:39, May 25 2020. g12b gb6bfa83 - gongwei.chen@droid11-sz

Board ID = 8
Set A53 clk to 24M
Set A73 clk to 24M
Set clk81 to 24M
A53 clk: 1200 MHz
A73 clk: 1200 MHz
CLK81: 166.6M
smccc: 00092010
board id: 8
Load FIP HDR DDR from SD, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0
Get wrong ddr fw magic! Error!!
fw parse done
PIEI prepare done
fastboot data verify
result: 255
Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
LPDDR4 probe

LPDDR4_PHY_V_0_1_22-Built : 16:01:44, May 25 2020. g12b gb6bfa83 - gongwei.chen@droid11-sz
ddr clk to 1608MHz

dmc_version 0001
Check phy result
INFO : End of CA training
INFO : End of initialization
INFO : Training has run successfully!
Check phy result
INFO : End of initialization
INFO : End of read enable training
INFO : End of fine write leveling
INFO : End of read dq deskew training
INFO : End of MPR read delay center optimization
INFO : End of Write leveling coarse delay
INFO : End of read delay center optimization
INFO : Training has run successfully!
Check phy result
INFO : End of initialization
INFO : End of MPR read delay center optimization
INFO : End of write delay center optimization
INFO : End of read delay center optimization
INFO : End of max read latency training
INFO : Training has run successfully!
1D training succeed
Check phy result
INFO : End of initialization
INFO : End of 2D read delay Voltage center optimization
INFO : End of 2D read delay Voltage center optimization
INFO : End of 2D write delay Voltage center optimization
INFO : End of 2D write delay Voltage center optimization
INFO : Training has run successfully!

soc_vref_reg_value 0x 00000027 00000027 00000028 00000027 00000026 00000024 00000026 00000026 00000028 00000026 00000024 00000025 00000026 00000027 00000025 00000027 00000026 00000027 00000028 00000028 00000027 00000027 00000027 00000027 00000029 00000027 00000029 00000027 000
dram_vref_reg_value 0x 00000012
2D training succeed
auto size-- 65535DDR cs0 size: 2048MB
DDR cs1 size: 2048MB
DMC_DDR_CTRL: 00e00024DDR size: 3928MB
cs0 DataBus test pass
cs1 DataBus test pass
cs0 AddrBus test pass
cs1 AddrBus test pass

non-sec scramble use zero key
ddr scramble enabled

100bdlr_step_size ps== 393
result report
boot times 0Enable ddr reg access
Load FIP HDR from SD, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
Load BL3X from SD, src: 0x00078200, des: 0x01768000, size: 0x0010ac00, part: 0
0.0;M3 CHK:0;cm4_sp_mode 0
[Image: g12b_v1.1.3394-7d43064d5 2020-05-07 15:37:11 gongwei.chen@droid11-sz]
OPS=0x10
ring efuse init
chipver efuse init
29 0b 10 00 01 0a 0c 00 00 09 35 38 47 47 52 50
[0.016082 Inits done]
secure task start!
high task start!
low task start!
run into bl31
NOTICE: BL31: v1.3(release):d9e1bbe85
NOTICE: BL31: Built : 19:07:43, Sep 7 2020
NOTICE: BL31: G12A normal boot!
NOTICE: BL31: BL33 decompress pass
ERROR: Error initializing runtime service opteed_fast

U-Boot 2015.01-g75547d1 (Feb 01 2021 - 15:07:59)

DRAM: 3.8 GiB
Relocation Offset is: d6d38000
mmu cfg end: 0xe0000000
mmu cfg end: 0xe0000000
spi_post_bind(spifc): req_seq = 0
register usb cfg[0][1] = 00000000d7e82570
aml_i2c_init_port init regs for 0
MCU version: 0x00 0x03
MCU version is to low! Doesn’t support froce boot from SD card.
NAND: get_sys_clk_rate_mtd() 292, clock setting 200!
bus cycle0: 6,timing: 7
NAND device id: 0 ff ff ff ff ff
No NAND device found!!!
nand init failed: -6
get_sys_clk_rate_mtd() 292, clock setting 200!
bus cycle0: 6,timing: 7
NAND device id: 0 ff ff ff ff ff
No NAND device found!!!
nand init failed: -6
MMC: aml_priv->desc_buf = 0x00000000d3d28a70
aml_priv->desc_buf = 0x00000000d3d2adb0
SDIO Port B: 0, SDIO Port C: 1
co-phase 0x3, tx-dly 0, clock 400000
co-phase 0x3, tx-dly 0, clock 400000
co-phase 0x3, tx-dly 0, clock 400000
emmc/sd response timeout, cmd8, cmd->cmdarg=0x1aa, status=0x3ff2800
emmc/sd response timeout, cmd55, cmd->cmdarg=0x0, status=0x3ff2800
co-phase 0x3, tx-dly 0, clock 400000
co-phase 0x1, tx-dly 0, clock 40000000
[set_emmc_calc_fixed_adj][875]find fixed adj_delay=20
[mmc_init] mmc init success
start dts,buffer=00000000d3d2d620,dt_addr=00000000d3d2d620
check_valid_dts: FDT_ERR_BADMAGIC
get_partition_from_dts() 92: ret -9
get_ptbl_from_dtb()-272: get partition table from dts faild
mmc_device_init()-1320: get partition table from dtb failed
get_ptbl_rsv()-494: magic faild MPT,
mmc_device_init()-1347: dtb&rsv are not exist, no LPT source
get partition info failed !!
Using default environment

In: serial
Out: serial
Err: serial
aml log : internal sys error!
reboot_mode=cold_boot
[store]To run cmd[emmc dtb_read 0x1000000 0x40000]
_verify_dtb_checksum()-3354: calc 0, store 0
update_dtb_info()-3462: cpy 1 is not valid
_verify_dtb_checksum()-3354: calc 0, store 0
update_dtb_info()-3462: cpy 0 is not valid
dtb_read()-3569: total valid 0
emmc - EMMC sub system

Usage:
emmc dtb_read addr size
emmc dtb_write addr size
emmc erase dtb
emmc erase key
emmc fastboot_read addr size
emmc fastboot_write addr size

aml_i2c_init_port init regs for 0
fusb302_init: Device ID: 0x91
[KM]Error:f[keymanage_dts_parse]L307:not a fdt at 0x0000000001000000
vpu: error: vpu: check dts: FDT_ERR_BADMAGIC, load default parameters
vpu: driver version: v20190313
vpu: detect chip type: 9
vpu: clk_level default: 7(666667000Hz), max: 7(666667000Hz)
vpu: clk_level = 7
vpu: vpu_power_on
vpu: set_vpu_clk
vpu: set clk: 666667000Hz, readback: 666666667Hz(0x100)
vpu: set_vpu_clk finish
vpu: vpu_module_init_config
vpp: vpp_init
vpp: vpp osd2 matrix rgb2yuv…
hdr_func 4, hdr_process_select 0x1
cvbs: cpuid:0x29
LCD_RESET PIN: 0
lcd: lcd_debug_print flag: 0
lcd: error: check dts: FDT_ERR_BADMAGIC, load default lcd parameters
lcd: detect mode: tablet, key_valid: 0
lcd: load config from bsp
lcd: use panel_type=lcd_1
lcd: bl: name: lcd_1, method: 1
lcd: bl: aml_bl_power_ctrl: 0
card in
co-phase 0x2, tx-dly 0, clock 400000
co-phase 0x2, tx-dly 0, clock 400000
co-phase 0x2, tx-dly 0, clock 400000
co-phase 0x2, tx-dly 0, clock 400000
co-phase 0x2, tx-dly 0, clock 40000000
[set_emmc_calc_fixed_adj][875]find fixed adj_delay=20
[mmc_init] mmc init success
Device: SDIO Port B
Manufacturer ID: 28
OEM: 4245
Name: SDU16
Tran Speed: 50000000
Rd Block Len: 512
SD version 3.0
High Capacity: Yes
Capacity: (0x3baf00000 Bytes) 14.9 GiB
mmc clock: 40000000
Bus Width: 4-bit
** Unrecognized filesystem type **
Net: use internal ethernet
--------ext_ethernet=0
+++++++++ext_ethernet=0
[KM]Error:f[keymanage_dts_get_key_device]L100:/unify not parsed yet!
[KM]Error:f[_get_km_ops_by_name]L240:key eth_exphy_para not know device 4
[KM]Error:f[key_unify_read]L304:key[eth_exphy_para] no cfg in dts
dwmac.ff3f0000 Waiting for PHY auto negotiation to complete… done
The Best Window is index 41
[KM]Error:f[keymanage_dts_get_key_device]L100:/unify not parsed yet!
[KM]Error:f[_get_km_ops_by_name]L240:key eth_exphy_para not know device 4
[KM]Error:f[key_unify_write]L271:key[eth_exphy_para] no cfg in dts
libfdt fdt_check_header(): FDT_ERR_BADMAGIC
No FDT memory address configured. Please configure
the FDT address via "fdt addr " command.
Aborting!
dwmac.ff3f0000[KM]Error:f[keymanage_dts_parse]L307:not a fdt at 0x0000000001000000

ramdump_init, add:0, size:0
CONFIG_AVB2: null
Start read misc partition datas!
Cannot find dev.
amlmmc cmd failed

store - STORE sub-system

Usage:
store init flag
store read name addr off|partition size
read ‘size’ bytes starting at offset ‘off’
to/from memory address ‘addr’, skipping bad blocks.
store write name addr off|partition size
write ‘size’ bytes starting at offset ‘off’
to/from memory address ‘addr’, skipping bad blocks.
store rom_write add off size.
write uboot to the boot device
store erase boot/data:
erase the area which is uboot or data
store erase partition <partition_name>:
erase the area which partition in u-boot
store erase dtb
store erase key
store disprotect key
store rom_protect on/off
store scrub off|partition size
scrub the area from offset and size
store dtb iread/read/write addr
read/write dtb, size is optional
store key read/write addr
read/write key, size is optional
store ddr_parameter read/write addr
read/write ddr parameter, size is optional
store mbr addr
update mbr/partition table by dtb
store bootlog
show boot logs

[burnup]Err:store_read_ops,L101:cmd failed, ret=1, [store read misc 0xd3d27090 0x0 0x820]
failed to store read misc.
info->magic =
info->version_major = 0
info->version_minor = 0
info->slots[0].priority = 0
info->slots[0].tries_remaining = 0
info->slots[0].successful_boot = 0
info->slots[1].priority = 0
info->slots[1].tries_remaining = 0
info->slots[1].successful_boot = 0
info->crc32 = 0
Magic is incorrect.
boot-info is invalid. Resetting.
save boot-info
info->magic =
info->version_major = 1
info->version_minor = 0
info->slots[0].priority = 15
info->slots[0].tries_remaining = 7
info->slots[0].successful_boot = 0
info->slots[1].priority = 14
info->slots[1].tries_remaining = 7
info->slots[1].successful_boot = 0
info->crc32 = -1075449479
Cannot find dev.
amlmmc cmd failed

store - STORE sub-system

Usage:
store init flag
store read name addr off|partition size
read ‘size’ bytes starting at offset ‘off’
to/from memory address ‘addr’, skipping bad blocks.
store write name addr off|partition size
write ‘size’ bytes starting at offset ‘off’
to/from memory address ‘addr’, skipping bad blocks.
store rom_write add off size.
write uboot to the boot device
store erase boot/data:
erase the area which is uboot or data
store erase partition <partition_name>:
erase the area which partition in u-boot
store erase dtb
store erase key
store disprotect key
store rom_protect on/off
store scrub off|partition size
scrub the area from offset and size
store dtb iread/read/write addr
read/write dtb, size is optional
store key read/write addr
read/write key, size is optional
store ddr_parameter read/write addr
read/write ddr parameter, size is optional
store mbr addr
update mbr/partition table by dtb
store bootlog
show boot logs

[burnup]Err:store_write_ops,L165:cmd [store write misc 0xd3d27090 0x0 0x820] failed active slot = 0

wipe_data=successful
wipe_cache=successful
upgrade_step=0
aml log : internal sys error!
reboot_mode:::: cold_boot
hpd_state=1
do_hpd_detect: hdmimode=1080p60hz
do_hpd_detect: colorattribute=444,8bit
Edid_MonitorCapable861: ycbcr444=1, ycbcr422=1
HDMI_EDID_BLOCK_TYPE_VENDER: pRXCap->ColorDeepSupport=0xb8
sink preferred_mode is 1080p60hz[16]
hdr mode is 0
dv mode is ver:0 len: 0
hdr10+ mode is 0
Edid_MonitorCapable861: ycbcr444=1, ycbcr422=1
HDMI_EDID_BLOCK_TYPE_VENDER: pRXCap->ColorDeepSupport=0xb8
read hdmichecksum 0x00000000, colorattribute 444,8bit
read hdmimode 1080p60hz, colorspace , colordepth
do_get_parse_edid: autoMode = false, manualMode=16
isYuv4kSink: false, maxTMDSRate=225
do_get_parse_edid: non-yuv4k sink: inColorSpace: HDMI_COLOR_FORMAT_RGB
do_get_parse_edid: default inColorDepth: HDMI_COLOR_DEPTH_24B
TV has changed, initial mode is: 1080p60hz attr: 444,8bit crc is :0xc60e0000
dolby_status 0
dolby_status 0
dolby_vision_process: hpd: dv disabled
Saving Environment to aml-storage…
get partition info failed !!
[OSD]check dts: FDT_ERR_BADMAGIC, load default fb_addr parameters
[OSD]set initrd_high: 0x3d800000
[OSD]fb_addr for logo: 0x3d800000
[OSD]check dts: FDT_ERR_BADMAGIC, load default fb_addr parameters
[OSD]fb_addr for logo: 0x3d800000
[OSD]VPP_OFIFO_SIZE:0xfff01fff
[CANVAS]canvas init
[CANVAS]addr=0x3d800000 width=3840, height=2160
Cannot find dev.
amlmmc cmd failed

store - STORE sub-system

Usage:
store init flag
store read name addr off|partition size
read ‘size’ bytes starting at offset ‘off’
to/from memory address ‘addr’, skipping bad blocks.
store write name addr off|partition size
write ‘size’ bytes starting at offset ‘off’
to/from memory address ‘addr’, skipping bad blocks.
store rom_write add off size.
write uboot to the boot device
store erase boot/data:
erase the area which is uboot or data
store erase partition <partition_name>:
erase the area which partition in u-boot
store erase dtb
store erase key
store disprotect key
store rom_protect on/off
store scrub off|partition size
scrub the area from offset and size
store dtb iread/read/write addr
read/write dtb, size is optional
store key read/write addr
read/write key, size is optional
store ddr_parameter read/write addr
read/write ddr parameter, size is optional
store mbr addr
update mbr/partition table by dtb
store bootlog
show boot logs

[burnup]Err:store_read_ops,L101:cmd failed, ret=1, [store read logo 0x3080000 0x0 0x2000]
Err imgread(L563):Fail to read 0x2000B from part[logo] at offset 0
There is no valid bmp file at the given address
[OSD]osd_hw.free_dst_data: 0,1919,0,1079
[OSD]osd1_update_disp_freescale_enable
cvbs: outputmode[1080p60hz] is invalid
vpp: vpp_matrix_update: 2
set hdmitx VIC = 16
aml_audio_init
config HPLL = 5940000 frac_rate = 1
HPLL: 0x3b3a04f7
HPLL: 0x1b3a04f7
HPLLv1: 0xdb3a04f7
config HPLL done
j = 6 vid_clk_div = 1
hdmitx: set enc for VIC: 16
hdmitx phy setting done
rx version is 1.4 or below div=10
hdmtix: set audio
hdmi_tx_set: save mode: 1080p60hz, attr: 444,8bit, hdmichecksum: 0xc60e0000
hdr_packet
vpp: hdr_policy = 0
vpp: Rx hdr_info.hdr_sup_eotf_smpte_st_2084 = 0
libfdt fdt_check_header(): FDT_ERR_BADMAGIC
No FDT memory address configured. Please configure
the FDT address via "fdt addr " command.
Aborting!
No FDT memory address configured. Please configure
the FDT address via "fdt addr " command.
Aborting!
normal power on
boot wol: disable
[reg_31] 0xd8a
[reg_16] 0x0
[reg_17] 0x7fff
[reg_19] 0x0
[reg_31] 0x0
[reg_31] 0xd40
[reg_22] 0x0
[reg_31] 0x0
saradc: 0x28b, hw_ver: 0x32 (VIM3.V12)

gpio: pin GPIOAO_7 (gpio 7) value is 1
libfdt fdt_check_header(): FDT_ERR_BADMAGIC
port mode is usb3.0
No FDT memory address configured. Please configure
the FDT address via "fdt addr " command.
Aborting!
No FDT memory address configured. Please configure
the FDT address via "fdt addr " command.
Aborting!
libfdt fdt_check_header(): FDT_ERR_BADMAGIC
No FDT memory address configured. Please configure
the FDT address via "fdt addr " command.
Aborting!
No FDT memory address configured. Please configure
the FDT address via "fdt addr " command.
Aborting!
Command: bcb uboot-command
Start read misc partition datas!
Cannot find dev.
amlmmc cmd failed

store - STORE sub-system

Usage:
store init flag
store read name addr off|partition size
read ‘size’ bytes starting at offset ‘off’
to/from memory address ‘addr’, skipping bad blocks.
store write name addr off|partition size
write ‘size’ bytes starting at offset ‘off’
to/from memory address ‘addr’, skipping bad blocks.
store rom_write add off size.
write uboot to the boot device
store erase boot/data:
erase the area which is uboot or data
store erase partition <partition_name>:
erase the area which partition in u-boot
store erase dtb
store erase key
store disprotect key
store rom_protect on/off
store scrub off|partition size
scrub the area from offset and size
store dtb iread/read/write addr
read/write dtb, size is optional
store key read/write addr
read/write key, size is optional
store ddr_parameter read/write addr
read/write ddr parameter, size is optional
store mbr addr
update mbr/partition table by dtb
store bootlog
show boot logs

[burnup]Err:store_read_ops,L101:cmd failed, ret=1, [store read misc 0xd3d27080 0x0 0x440]
failed to store read misc.
bcb - bcb

Usage:
bcb
This command will run some commands which saved in misc
partition by mark to decide whether execute command!
Command format:
bcb bcb_mark
Example:
/dev/block/misc partiton is saved some contents:
uboot-command
N/A
setenv aa 11;setenv bb 22;setenv cc 33;saveenv;
So you can execute command: bcb uboot-command

Hit Enter or space or Ctrl+C key to stop autoboot – : 0
cfgload: start …
cfgload: reading /boot.ini from mmc 0:1 …
** No partition table - mmc 0 **
cfgload: no /boot.ini or empty file on mmc 0:1
cfgload: reading /boot.ini from mmc 1:1 …
** No partition table - mmc 1 **
cfgload: no /boot.ini or empty file on mmc 1:1
cfgload: reading /boot/boot.ini from mmc 1:5 …
** No partition table - mmc 1 **
cfgload: no /boot/boot.ini or empty file on mmc 1:5
cfgload: failed to read boot.ini on all partitions!
CONFIG_SYSTEM_AS_ROOT: systemroot
system_mode: 1
active_slot: normal
Cannot find dev.
amlmmc cmd failed

store - STORE sub-system

Usage:
store init flag
store read name addr off|partition size
read ‘size’ bytes starting at offset ‘off’
to/from memory address ‘addr’, skipping bad blocks.
store write name addr off|partition size
write ‘size’ bytes starting at offset ‘off’
to/from memory address ‘addr’, skipping bad blocks.
store rom_write add off size.
write uboot to the boot device
store erase boot/data:
erase the area which is uboot or data
store erase partition <partition_name>:
erase the area which partition in u-boot
store erase dtb
store erase key
store disprotect key
store rom_protect on/off
store scrub off|partition size
scrub the area from offset and size
store dtb iread/read/write addr
read/write dtb, size is optional
store key read/write addr
read/write key, size is optional
store ddr_parameter read/write addr
read/write ddr parameter, size is optional
store mbr addr
update mbr/partition table by dtb
store bootlog
show boot logs

[burnup]Err:store_read_ops,L101:cmd failed, ret=1, [store read boot 0x3080000 0x0 0x100000]
Err imgread(L338):Fail to read 0x100000B from part[boot] at offset 0

InUsbBurn
wait for phy ready count is 0
noSof
sof timeout, reset usb phy tuning
Device: SDIO Port B
Manufacturer ID: 28
OEM: 4245
Name: SDU16
Tran Speed: 50000000
Rd Block Len: 512
SD version 3.0
High Capacity: Yes
Capacity: (0x3baf00000 Bytes) 14.9 GiB
mmc clock: 40000000
Bus Width: 4-bit
** Unrecognized filesystem type **
Device: SDIO Port B
Manufacturer ID: 28
OEM: 4245
Name: SDU16
Tran Speed: 50000000
Rd Block Len: 512
SD version 3.0
High Capacity: Yes
Capacity: (0x3baf00000 Bytes) 14.9 GiB
mmc clock: 40000000
Bus Width: 4-bit
** Unrecognized filesystem type **
** Unrecognized filesystem type **
(Re)start USB…
USB0: USB3.0 XHCI init start
Register 3000140 NbrPorts 2
Starting the controller
USB XHCI 1.10
scanning bus 0 for devices… 3 USB Device(s) found
scanning usb for storage devices… 0 Storage Device(s) found
** Bad device usb 0 **
** Bad device usb 0 **
Start read misc partition datas!
Cannot find dev.
amlmmc cmd failed

store - STORE sub-system

Usage:
store init flag
store read name addr off|partition size
read ‘size’ bytes starting at offset ‘off’
to/from memory address ‘addr’, skipping bad blocks.
store write name addr off|partition size
write ‘size’ bytes starting at offset ‘off’
to/from memory address ‘addr’, skipping bad blocks.
store rom_write add off size.
write uboot to the boot device
store erase boot/data:
erase the area which is uboot or data
store erase partition <partition_name>:
erase the area which partition in u-boot
store erase dtb
store erase key
store disprotect key
store rom_protect on/off
store scrub off|partition size
scrub the area from offset and size
store dtb iread/read/write addr
read/write dtb, size is optional
store key read/write addr
read/write key, size is optional
store ddr_parameter read/write addr
read/write ddr parameter, size is optional
store mbr addr
update mbr/partition table by dtb
store bootlog
show boot logs

[burnup]Err:store_read_ops,L101:cmd failed, ret=1, [store read misc 0xd3d26b90 0x0 0x820]
failed to store read misc.
info->magic =
info->version_major = 0
info->version_minor = 0
info->slots[0].priority = 0
info->slots[0].tries_remaining = 0
info->slots[0].successful_boot = 0
info->slots[1].priority = 0
info->slots[1].tries_remaining = 0
info->slots[1].successful_boot = 0
info->crc32 = 0
Magic is incorrect.
boot-info is invalid. Resetting.
save boot-info
info->magic =
info->version_major = 1
info->version_minor = 0
info->slots[0].priority = 15
info->slots[0].tries_remaining = 7
info->slots[0].successful_boot = 0
info->slots[1].priority = 14
info->slots[1].tries_remaining = 7
info->slots[1].successful_boot = 0
info->crc32 = -1075449479
Cannot find dev.
amlmmc cmd failed

store - STORE sub-system

Usage:
store init flag
store read name addr off|partition size
read ‘size’ bytes starting at offset ‘off’
to/from memory address ‘addr’, skipping bad blocks.
store write name addr off|partition size
write ‘size’ bytes starting at offset ‘off’
to/from memory address ‘addr’, skipping bad blocks.
store rom_write add off size.
write uboot to the boot device
store erase boot/data:
erase the area which is uboot or data
store erase partition <partition_name>:
erase the area which partition in u-boot
store erase dtb
store erase key
store disprotect key
store rom_protect on/off
store scrub off|partition size
scrub the area from offset and size
store dtb iread/read/write addr
read/write dtb, size is optional
store key read/write addr
read/write key, size is optional
store ddr_parameter read/write addr
read/write ddr parameter, size is optional
store mbr addr
update mbr/partition table by dtb
store bootlog
show boot logs

[burnup]Err:store_write_ops,L165:cmd [store write misc 0xd3d26b90 0x0 0x820] failed active slot = 0
active_slot: normal
Cannot find dev.
amlmmc cmd failed

store - STORE sub-system

Usage:
store init flag
store read name addr off|partition size
read ‘size’ bytes starting at offset ‘off’
to/from memory address ‘addr’, skipping bad blocks.
store write name addr off|partition size
write ‘size’ bytes starting at offset ‘off’
to/from memory address ‘addr’, skipping bad blocks.
store rom_write add off size.
write uboot to the boot device
store erase boot/data:
erase the area which is uboot or data
store erase partition <partition_name>:
erase the area which partition in u-boot
store erase dtb
store erase key
store disprotect key
store rom_protect on/off
store scrub off|partition size
scrub the area from offset and size
store dtb iread/read/write addr
read/write dtb, size is optional
store key read/write addr
read/write key, size is optional
store ddr_parameter read/write addr
read/write ddr parameter, size is optional
store mbr addr
update mbr/partition table by dtb
store bootlog
show boot logs

[burnup]Err:store_read_ops,L101:cmd failed, ret=1, [store read recovery 0x3080000 0x0 0x100000]
Err imgread(L338):Fail to read 0x100000B from part[recovery] at offset 0
kvim3#

Hello, Had you just flashed the image, or did the issue just start after some time?

What Android version(image)?

What are you using to power your VIM3?

I am running https://dl.khadas.com/Firmware/VIM3/Android/VIM3_Andorid.Pie_V210128.raw.img.xz

I am using a 2.5A USB-C.
The board came as it is with a reset loop.
I think the problem is the EMMC having no partitions:

[set_emmc_calc_fixed_adj][875]find fixed adj_delay=20
[mmc_init] mmc init success
Device: SDIO Port B
Manufacturer ID: 28
OEM: 4245
Name: SDU16
Tran Speed: 50000000
Rd Block Len: 512
SD version 3.0
High Capacity: Yes
Capacity: (0x3baf00000 Bytes) 14.9 GiB
mmc clock: 40000000
Bus Width: 4-bit
** Unrecognized filesystem type **
Net: use internal ethernet
--------ext_ethernet=0
+++++++++ext_ethernet=0
[KM]Error:f[keymanage_dts_get_key_device]L100:/unify not parsed yet!
[KM]Error:f[_get_km_ops_by_name]L240:key eth_exphy_para not know device 4

[KM]Error:f[key_unify_read]L304:key[eth_exphy_para] no cfg in dts
dwmac.ff3f0000 Waiting for PHY auto negotiation to complete… done
The Best Window is index 41
[KM]Error:f[keymanage_dts_get_key_device]L100:/unify not parsed yet!
[KM]Error:f[_get_km_ops_by_name]L240:key eth_exphy_para not know device 4
[KM]Error:f[key_unify_write]L271:key[eth_exphy_para] no cfg in dts
libfdt fdt_check_header(): FDT_ERR_BADMAGIC
No FDT memory address configured. Please configure
the FDT address via "fdt addr " command.
Aborting!
dwmac.ff3f0000[KM]Error:f[keymanage_dts_parse]L307:not a fdt at 0x0000000001000000
ramdump_init, add:0, size:0
CONFIG_AVB2: null
Start read misc partition datas!
Cannot find dev.
amlmmc cmd failed

Not sure that I am using amlmmc correctly but this is what’s showing

kvim3#amlmmc part 0

Unknown partition table

kvim3#amlmmc part 1

Unknown partition table

amlmmc env
herh
get partition info failed !!
Using default environment

amlmmc list
SDIO Port B: 0
SDIO Port C: 1

afaik the installer tries the “store” command and that fails with:

kvim3#store init
XXXXXXX======enter EMMC boot======XXXXXX
co-phase 0x1, tx-dly 0, clock 40000000
co-phase 0x1, tx-dly 0, clock 40000000
co-phase 0x3, tx-dly 0, clock 400000
emmc/sd response timeout, cmd8, cmd->cmdarg=0x1aa, status=0x3bf2800
emmc/sd response timeout, cmd55, cmd->cmdarg=0x0, status=0x3bf2800
co-phase 0x3, tx-dly 0, clock 400000
co-phase 0x1, tx-dly 0, clock 40000000
[set_emmc_calc_fixed_adj][875]find fixed adj_delay=20
[mmc_init] mmc init success
start dts,buffer=00000000d3d53bf0,dt_addr=00000000d3d53bf0
check_valid_dts: FDT_ERR_BADMAGIC
get_partition_from_dts() 92: ret -9
get_ptbl_from_dtb()-272: get partition table from dts faild
mmc_device_init()-1320: get partition table from dtb failed
get_ptbl_rsv()-494: magic faild MPT,
mmc_device_init()-1347: dtb&rsv are not exist, no LPT source
switch to partitions #0, OK
mmc1(part 0) is current device
Device: SDIO Port C
Manufacturer ID: 15
OEM: 100
Name: BJTD4
Tran Speed: 52000000
Rd Block Len: 512
MMC version 5.1
High Capacity: Yes
Capacity: (0x747c00000 Bytes) 29.1 GiB
mmc clock: 40000000
Bus Width: 8-bit

Just tried the latest krescue from: https://dl.khadas.com/Firmware/Krescue/dump/VIM3.krescue.sd.img.gz

same reset loop as above.

try another one

store init 3 

Had this before but here we go again:

kvim3#store init 3

XXXXXXX======enter EMMC boot======XXXXXX
co-phase 0x1, tx-dly 0, clock 40000000
co-phase 0x1, tx-dly 0, clock 40000000
co-phase 0x3, tx-dly 0, clock 400000
emmc/sd response timeout, cmd8, cmd->cmdarg=0x1aa, status=0x3bf2800
emmc/sd response timeout, cmd55, cmd->cmdarg=0x0, status=0x3bf2800
co-phase 0x3, tx-dly 0, clock 400000
co-phase 0x1, tx-dly 0, clock 40000000
[set_emmc_calc_fixed_adj][875]find fixed adj_delay=20
[mmc_init] mmc init success
start dts,buffer=00000000d3d53b30,dt_addr=00000000d3d53b30
check_valid_dts: FDT_ERR_BADMAGIC
get_partition_from_dts() 92: ret -9
get_ptbl_from_dtb()-272: get partition table from dts faild
mmc_device_init()-1320: get partition table from dtb failed
get_ptbl_rsv()-494: magic faild MPT,
mmc_device_init()-1347: dtb&rsv are not exist, no LPT source
switch to partitions #0, OK
mmc1(part 0) is current device
Device: SDIO Port C
Manufacturer ID: 15
OEM: 100
Name: BJTD4
Tran Speed: 52000000
Rd Block Len: 512
MMC version 5.1
High Capacity: Yes
Capacity: (0x747c00000 Bytes) 29.1 GiB
mmc clock: 40000000
Bus Width: 8-bit
[store]amlmmc erase 1Cannot find dev.

try https://dl.khadas.com/Firmware/Krescue/system/README-rescue-boot.txt

  • unplug usb cable
  • insert SD card with Krescue
  • press and hold POWER_KEY
  • plug usb cable and wait LED blinking after u can unpress POWER_KEY
  • ok Krescye system bootup from SD

and try clean MMC via krescue

Hello there,

The krescue system is also going in a loop:

reset...
G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:0;READ:0;CHK:1F;READ:0;CHK:1F;READ:0;CHK:1F;SD?:0;SD:0;READ:0;0.
bl2_stage_init 0x01
bl2_stage_init 0x81
hw id: 0x0000 - pwm id 0x01
bl2_stage_init 0xc1
bl2_stage_init 0x02

no sdio debug board detected 
L0:00000000
L1:20000703
L2:00008067
L3:14000000
B2:00402000
B1:e0f83180

TE: 365469

BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz

Board ID = 8
Set A53 clk to 24M
Set A73 clk to 24M
Set clk81 to 24M
A53 clk: 1200 MHz
A73 clk: 1200 MHz
CLK81: 166.6M
smccc: 0005db7b
DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
board id: 8
Load FIP HDR from SD, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0
fw parse done
Load ddrfw from SD, src: 0x00060200, des: 0xfffd0000, size: 0x0000c000, part: 0
Load ddrfw from SD, src: 0x00038200, des: 0xfffd0000, size: 0x00004000, part: 0
PIEI prepare done
fastboot data load
fastboot data verify
verify result: 266
Cfg max: 4, cur: 1. Board id: 255. Force loop cfg
LPDDR4 probe
ddr clk to 1608MHz
Load ddrfw from SD, src: 0x0003c200, des: 0xfffd0000, size: 0x0000c000, part: 0

dmc_version 0001
Check phy result
INFO : End of CA training
INFO : End of initialization
INFO : Training has run successfully!
Check phy result
INFO : End of initialization
INFO : End of read enable training
INFO : End of fine write leveling
INFO : End of Write leveling coarse delay
INFO : Training has run successfully!
Check phy result
INFO : End of initialization
INFO : End of read dq deskew training
INFO : End of MPR read delay center optimization
INFO : End of write delay center optimization
INFO : End of read delay center optimization
INFO : End of max read latency training
INFO : Training has run successfully!
1D training succeed
Load ddrfw from SD, src: 0x00048200, des: 0xfffd0000, size: 0x0000c000, part: 0
Check phy result
INFO : End of initialization
INFO : End of 2D read delay Voltage center optimization
INFO : End of 2D read delay Voltage center optimization
INFO : End of 2D write delay Voltage center optimization
INFO : End of 2D write delay Voltage center optimization
INFO : Training has run successfully!

channel==0
RxClkDly_Margin_A0==97 ps 10
TxDqDly_Margin_A0==97 ps 10
RxClkDly_Margin_A1==58 ps 6
TxDqDly_Margin_A1==106 ps 11
TrainedVREFDQ_A0==27
TrainedVREFDQ_A1==27
VrefDac_Margin_A0==27
DeviceVref_Margin_A0==26
VrefDac_Margin_A1==31
DeviceVref_Margin_A1==27


channel==1
RxClkDly_Margin_A0==97 ps 10
TxDqDly_Margin_A0==106 ps 11
RxClkDly_Margin_A1==97 ps 10
TxDqDly_Margin_A1==106 ps 11
TrainedVREFDQ_A0==25
TrainedVREFDQ_A1==26
VrefDac_Margin_A0==27
DeviceVref_Margin_A0==24
VrefDac_Margin_A1==28
DeviceVref_Margin_A1==25

 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004 

soc_vref_reg_value 0x 00000027 00000027 00000028 00000027 00000026 00000024 00000026 00000026 00000027 00000026 00000024 00000026 00000026 00000027 00000025 00000028 00000026 00000027 00000028 00000028 00000027 00000027 00000027 00000027 00000029 00000027 00000029 00000027 0003
2D training succeed
aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
auto size-- 65535DDR cs0 size: 2048MB
DDR cs1 size: 2048MB
DMC_DDR_CTRL: 00e00024DDR size: 3928MB
cs0 DataBus test pass
cs1 DataBus test pass
cs0 AddrBus test pass
cs1 AddrBus test pass

100bdlr_step_size ps== 388
result report
boot times 0Enable ddr reg access
Load FIP HDR from SD, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
FIP HDR CHK: 0x00000064 ADDR 0x01700000
reset...
G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:0;READ:0;CHK:1F;READ:0;CHK:1F;READ:0;CHK:1F;SD?:0;SD:0;READ:0;0.

Sorry guys, in the end it was a bad older 256MB sd-card which I thought it might be enough for krescue to run on. Problem solved by using a current sd-card. Lesson learned.

Glad you found a solution.
Have fun.:slightly_smiling_face: