Mainline u-boot for khadas sbc

I would like to celebrate the constant work of the khadas team and of all the developers helping them.
Now that we finally have working and stable uboot and mainline linux kernel, hooray, well done, kudos, and relax !
We can sincerly begin to forget the bad old days (of android in the emmc as the starting point for everything else) and the weird actions needed back then (boot to SD , use some script to rewrite emmc).

I hope all this will help Manjaro (and Arch based distro ) manage to attract more users, especially on the khadas boards we choose to follow (since the very beginning, for a few of us).

3 Likes

Thanks you hyphop!!

I have flashed mainline u-boot in the SPI and now I can boot GNU/Linux from the SD and Android from EMMC. Also the green screen problem and the USB keyboard/mouse disabled have gone.

YES its good solution ! just change kbi bootmode from SPI to EMMC and back (mainline uboot start sd / usb and vendor uboot start mmc )

PS: another questions why u still need android :wink: ?

Hello @hyphop

I am back with some debugging and booting issues hahaha.
VIm1 works fine no issues at all even with android on emmc.
Vim2 works too but need to enter multiboot mode for every boot.
Vim3 gets stuck in uboot.env not found error.

This post is for vim3.

  1. I erase my emmc using store init 3 as explained on Khadas Docs
  2. Created Manjaro OS image with Mainline uboot. Mainline uboot = VIM3.u-boot.sd.bin from khadas download page.
  3. Tried to boot from sd card with Manjaro OS mainline uboot flashed on sd card.

Here is the uart output for clear information.

                                                                                       
G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:0;READ:0;CHK:1F;READ:0;CHK:
1F;READ:0;CHK:1F;SD?:0;SD:0;READ:0;0.                                                  
bl2_stage_init 0x01                                                                    
bl2_stage_init 0x81                                                                    
hw id: 0x0000 - pwm id 0x01                                                            
bl2_stage_init 0xc1                                                                    
bl2_stage_init 0x02                                                                    
                                                                                       
no sdio debug board detected                                                           
L0:00000000                                                                            
L1:20000703                                                                            
L2:00008067                                                                            
L3:14000000                                                                            
B2:00402000                                                                            
B1:e0f83180                                                                            
                                                                                       
TE: 451538                                                                             
                                                                                       
BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz                
                                                                                       
Board ID = 8                                                                           
Set A53 clk to 24M                                                                     
Set A73 clk to 24M                                                                     
Set clk81 to 24M                                                                       
A53 clk: 1200 MHz                                                                      
A73 clk: 1200 MHz                                                                      
CLK81: 166.6M                                                                          
smccc: 00072bb0                                                                        
DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01                
board id: 8                                                                            
Load FIP HDR from SD, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0      
fw parse done                                                                          
Load ddrfw from SD, src: 0x00060200, des: 0xfffd0000, size: 0x0000c000, part: 0        
Load ddrfw from SD, src: 0x00038200, des: 0xfffd0000, size: 0x00004000, part: 0        
PIEI prepare done                                                                      
fastboot data load                                                                     
fastboot data verify                                                                   
verify result: 266                                                                     
Cfg max: 4, cur: 1. Board id: 255. Force loop cfg                                      
LPDDR4 probe                                                                           
ddr clk to 1608MHz                                                                     
Load ddrfw from SD, src: 0x0003c200, des: 0xfffd0000, size: 0x0000c000, part: 0        
                                                                                       
dmc_version 0001                                                                       
Check phy result                                                                       
INFO : End of CA training                                                              
INFO : End of initialization                                                           
INFO : Training has run successfully!                                                  
Check phy result                                                                       
INFO : End of initialization                                                           
INFO : End of read enable training                                                     
INFO : End of fine write leveling                                                      
INFO : End of Write leveling coarse delay                                              
INFO : Training has run successfully!                                                  
Check phy result                                                                       
INFO : End of initialization                                                           
INFO : End of read dq deskew training                                                  
INFO : End of MPR read delay center optimization                                       
INFO : End of write delay center optimization                                          
INFO : End of read delay center optimization                                           
INFO : End of max read latency training                                                
INFO : Training has run successfully!                                                  
1D training succeed                                                                    
Load ddrfw from SD, src: 0x00048200, des: 0xfffd0000, size: 0x0000c000, part: 0        
Check phy result                                                                       
INFO : End of initialization                                                           
INFO : End of 2D read delay Voltage center optimization                                
INFO : End of 2D read delay Voltage center optimization                                
INFO : End of 2D write delay Voltage center optimization                               
INFO : End of 2D write delay Voltage center optimization                               
INFO : Training has run successfully!                                                  
                                                                                       
channel==0                                                                             
RxClkDly_Margin_A0==97 ps 10                                                           
TxDqDly_Margin_A0==106 ps 11                                                           
RxClkDly_Margin_A1==58 ps 6                                                            
TxDqDly_Margin_A1==106 ps 11                                                           
TrainedVREFDQ_A0==27                                                                   
TrainedVREFDQ_A1==27                                                                   
VrefDac_Margin_A0==28                                                                  
DeviceVref_Margin_A0==26                                                               
VrefDac_Margin_A1==30                                                                  
DeviceVref_Margin_A1==27                                                               
                                                                                       
                                                                                       
channel==1                                                                             
RxClkDly_Margin_A0==97 ps 10                                                           
TxDqDly_Margin_A0==106 ps 11                                                           
RxClkDly_Margin_A1==97 ps 10                                                           
TxDqDly_Margin_A1==106 ps 11                                                           
TrainedVREFDQ_A0==26                                                                   
TrainedVREFDQ_A1==26                                                                   
VrefDac_Margin_A0==28                                                                  
DeviceVref_Margin_A0==25                                                               
VrefDac_Margin_A1==26                                                                  
DeviceVref_Margin_A1==25                                                               
                                                                                       
 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004                                 
                                                                                       
soc_vref_reg_value 0x 00000027 00000027 00000026 00000025 00000027 00000025 00000025 00
000025 00000025 00000026 00000027 00000026 00000025 00000026 00000025 00000025 00000025
 00000025 00000025 00000025 00000023 00000026 00000026 00000025 00000025 00000025 00000
027 00000027 00000025 00000024 00000027 00000027 dram_vref_reg_value 0x 00000013       
2D training succeed                                                                    
aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19                
auto size-- 65535DDR cs0 size: 2048MB                                                  
DDR cs1 size: 2048MB                                                                   
DMC_DDR_CTRL: 00e00024DDR size: 3928MB                                                 
cs0 DataBus test pass                                                                  
cs1 DataBus test pass                                                                  
cs0 AddrBus test pass                                                                  
cs1 AddrBus test pass                                                                  
                                                                                       
100bdlr_step_size ps== 450                                                             
result report                                                                          
boot times 0Enable ddr reg access                                                      
Load FIP HDR from SD, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0      
Load BL3X from SD, src: 0x00078200, des: 0x01768000, size: 0x000a0000, part: 0         
0.0;M3 CHK:0;cm4_sp_mode 0                                                             
MVN_1=0x00000000                                                                       
MVN_2=0x00000000                                                                       
[Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]               
OPS=0x10                                                                               
ring efuse init                                                                        
chipver efuse init                                                                     
29 0b 10 00 01 1d 0a 00 00 03 35 38 47 47 52 50                                        
[0.018961 Inits done]                                                                  
secure task start!                                                                     
high task start!                                                                       
low task start!                                                                        
run into bl31                                                                          
NOTICE:  BL31: v1.3(release):4fc40b1                                                   
NOTICE:  BL31: Built : 15:58:17, May 22 2019                                           
NOTICE:  BL31: G12A normal boot!                                                       
NOTICE:  BL31: BL33 decompress pass                                                    
ERROR:   Error initializing runtime service opteed_fast                                
                                                                                       
                                                                                       
U-Boot 2020.04 (Jul 16 2020 - 16:51:18 +0900) khadas-vim3                              
                                                                                       
Model: Khadas VIM3                                                                     
SoC:   Amlogic Meson G12B (A311D) Revision 29:b (10:2)                                 
DRAM:  3.8 GiB                                                                         
MMC:   sd@ffe03000: 0, sd@ffe05000: 1, mmc@ffe07000: 2                                 
Loading Environment from FAT... detect... booted from sd...                            
"uboot.env" not found on mmc-1:1... OK                                                 

I cannot enter in uboot cli to check env it is using

Please advice what I am missing here.

Thanks.

UPDATE:
I tried krescue image and it is the same.

G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:0;READ:0;CHK:1F;G12B:BL:6e7
c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:0;READ:0;CHK:1F;READ:0;CHK:1F;READ:0;C
HK:1F;SD?:0;SD:0;READ:0;0.                                                             
bl2_stage_init 0x01                                                                    
bl2_stage_init 0x81                                                                    
hw id: 0x0000 - pwm id 0x01                                                            
bl2_stage_init 0xc1                                                                    
bl2_stage_init 0x02                                                                    
                                                                                       
no sdio debug board detected                                                           
L0:00000000                                                                            
L1:20000703                                                                            
L2:00008067                                                                            
L3:14000000                                                                            
B2:00402000                                                                            
B1:e0f83180                                                                            
                                                                                       
TE: 496423                                                                             
                                                                                       
BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz                
                                                                                       
Board ID = 8                                                                           
Set A53 clk to 24M                                                                     
Set A73 clk to 24M                                                                     
Set clk81 to 24M                                                                       
A53 clk: 1200 MHz                                                                      
A73 clk: 1200 MHz                                                                      
CLK81: 166.6M                                                                          
smccc: 0007db05                                                                        
DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01                
board id: 8                                                                            
Load FIP HDR from SD, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0      
fw parse done                                                                          
Load ddrfw from SD, src: 0x00060200, des: 0xfffd0000, size: 0x0000c000, part: 0        
Load ddrfw from SD, src: 0x00038200, des: 0xfffd0000, size: 0x00004000, part: 0        
PIEI prepare done                                                                      
fastboot data load                                                                     
fastboot data verify                                                                   
verify result: 266                                                                     
Cfg max: 4, cur: 1. Board id: 255. Force loop cfg                                      
LPDDR4 probe                                                                           
ddr clk to 1608MHz                                                                     
Load ddrfw from SD, src: 0x0003c200, des: 0xfffd0000, size: 0x0000c000, part: 0        
                                                                                       
dmc_version 0001                                                                       
Check phy result                                                                       
INFO : End of CA training                                                              
INFO : End of initialization                                                           
INFO : Training has run successfully!                                                  
Check phy result                                                                       
INFO : End of initialization                                                           
INFO : End of read enable training                                                     
INFO : End of fine write leveling                                                      
INFO : End of Write leveling coarse delay                                              
INFO : Training has run successfully!                                                  
Check phy result                                                                       
INFO : End of initialization                                                           
INFO : End of read dq deskew training                                                  
INFO : End of MPR read delay center optimization                                       
INFO : End of write delay center optimization                                          
INFO : End of read delay center optimization                                           
INFO : End of max read latency training                                                
INFO : Training has run successfully!                                                  
1D training succeed                                                                    
Load ddrfw from SD, src: 0x00048200, des: 0xfffd0000, size: 0x0000c000, part: 0        
Check phy result                                                                       
INFO : End of initialization                                                           
INFO : End of 2D read delay Voltage center optimization                                
INFO : End of 2D read delay Voltage center optimization                                
INFO : End of 2D write delay Voltage center optimization                               
INFO : End of 2D write delay Voltage center optimization                               
INFO : Training has run successfully!                                                  
                                                                                       
channel==0                                                                             
RxClkDly_Margin_A0==87 ps 9                                                            
TxDqDly_Margin_A0==106 ps 11                                                           
RxClkDly_Margin_A1==77 ps 8                                                            
TxDqDly_Margin_A1==97 ps 10                                                            
TrainedVREFDQ_A0==26                                                                   
TrainedVREFDQ_A1==27                                                                   
VrefDac_Margin_A0==29                                                                  
DeviceVref_Margin_A0==26                                                               
VrefDac_Margin_A1==29                                                                  
DeviceVref_Margin_A1==27                                                               
                                                                                       
                                                                                       
channel==1                                                                             
RxClkDly_Margin_A0==106 ps 11                                                          
TxDqDly_Margin_A0==106 ps 11                                                           
RxClkDly_Margin_A1==97 ps 10                                                           
TxDqDly_Margin_A1==106 ps 11                                                           
TrainedVREFDQ_A0==26                                                                   
TrainedVREFDQ_A1==26                                                                   
VrefDac_Margin_A0==28                                                                  
DeviceVref_Margin_A0==25                                                               
VrefDac_Margin_A1==27                                                                  
DeviceVref_Margin_A1==25                                                               
                                                                                       
 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004                                 
                                                                                       
soc_vref_reg_value 0x 00000028 00000027 00000026 00000025 00000027 00000025 00000025 00
000025 00000025 00000026 00000027 00000026 00000025 00000026 00000025 00000025 00000025
 00000025 00000025 00000025 00000023 00000026 00000026 00000025 00000025 00000025 00000
027 00000027 00000025 00000024 00000027 00000027 dram_vref_reg_value 0x 00000013       
2D training succeed                                                                    
aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19                
auto size-- 65535DDR cs0 size: 2048MB                                                  
DDR cs1 size: 2048MB                                                                   
DMC_DDR_CTRL: 00e00024DDR size: 3928MB                                                 
cs0 DataBus test pass                                                                  
cs1 DataBus test pass                                                                  
cs0 AddrBus test pass                                                                  
cs1 AddrBus test pass                                                                  
                                                                                       
100bdlr_step_size ps== 450                                                             
result report                                                                          
boot times 0Enable ddr reg access                                                      
Load FIP HDR from SD, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0      
Load BL3X from SD, src: 0x00078200, des: 0x01768000, size: 0x000a0000, part: 0         
0.0;M3 CHK:0;cm4_sp_mode 0                                                             
MVN_1=0x00000000                                                                       
MVN_2=0x00000000                                                                       
[Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]               
OPS=0x10                                                                               
ring efuse init                                                                        
chipver efuse init                                                                     
29 0b 10 00 01 1d 0a 00 00 03 35 38 47 47 52 50                                        
[0.018960 Inits done]                                                                  
secure task start!                                                                     
high task start!                                                                       
low task start!                                                                        
run into bl31                                                                          
NOTICE:  BL31: v1.3(release):4fc40b1                                                   
NOTICE:  BL31: Built : 15:58:17, May 22 2019                                           
NOTICE:  BL31: G12A normal boot!                                                       
NOTICE:  BL31: BL33 decompress pass                                                    
ERROR:   Error initializing runtime service opteed_fast                                
                                                                                       
                                                                                       
U-Boot 2020.04 (Jul 03 2020 - 16:33:07 +0900) khadas-vim3                              
                                                                                       
Model: Khadas VIM3                                                                     
SoC:   Amlogic Meson G12B (A311D) Revision 29:b (10:2)                                 
DRAM:  3.8 GiB                                                                         
MMC:   sd@ffe03000: 0, sd@ffe05000: 1, mmc@ffe07000: 2                                 
Loading Environment from FAT... detect... booted from sd...                            
"uboot.env" not found on mmc-1:1... OK  

Please advice.

Thanks.

its not error it just warning - and told about 1st fat partition not found (uboot env saved in restored to
uboot.env on 1st fat partition ) but its not must be a problem - if uboot.env cant loaded booting must continue ayway

anyway if you booting was freezed in uboot stage - i must reproduce your situation and try understand what a problem!!!

Vim2 works too but need to enter multiboot mode for every boot.

didnt undestand - what is multiboot mode ? ;)))

I tried krescue image and it is the same.

yes its must be same as https://dl.khadas.com/Firmware/uboot/mainline/

PS: last uboot images - can goto cli mode (by SPACE or CRTL+C - not by ANY key as was before )

PSS: try to undestand whats wrong !!! its just for checking

  1. write last openwrt image to VIM3 via krescue to emmc - CHECK how its works
  2. write only uboot mainline via same krescue - write openwrt sd image to sd or usb https://dl.khadas.com/Firmware/openwrt/ - CHECK how its works
  3. clear emmc and start openwrt from sd - - CHECK how its works

for me all steps was works fine - and its same mainline uboot

PSSSS: write me about your results - goodluck

Leave this for now :wink:

I tried krescue and it is stuck on same place uboot.env not found but when I try to boot from sd card with Libreelec using Mainline uboot it boot pass this error.

Yes ofcourse I tried SPACE but it doesn’t even reach the uboot cli position for it to enter into uboot cli :frowning:

Only If I can get krescue to boot, as I said krescue also get stuck at the same stage with uboot.env not found.

try another way https://dl.khadas.com/Firmware/uboot/mainline/VIM3L.uboot-mainline.emmc.aml.img
write via aml-burn-tool - may be it can help

without sd cards and any usb - uboot still freezed ?

My emmc is blank as I erased it completely,
Flashed krescue in sdcard
Insert sd card in Vim3
Stuck at uboot.env not found.

OK! write sd openwrt image https://dl.khadas.com/Firmware/openwrt/ - i have test it many times and its works for me (any combinations)
WRITE ME BACK YOUR RESULTS

did u try other SD card ?

PS: try without usb keyboard !!!

Sure.
I only have usb-c power and sd card with the vim3 openwrt image.
Log below.

Press CTRL-A Z for help on special keys

G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:0;READ:0;CHK:1F;READ:0;CHK.
bl2_stage_init 0x01
bl2_stage_init 0x81
hw id: 0x0000 - pwm id 0x01
bl2_stage_init 0xc1
bl2_stage_init 0x02

no sdio debug board detected 
L0:00000000
L1:20000703
L2:00008067
L3:14000000
B2:00402000
B1:e0f83180                                                                            
                                                                                       
TE: 311970                                                                             
                                                                                       
BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz                
                                                                                       
Board ID = 8                                                                           
Set A53 clk to 24M                                                                     
Set A73 clk to 24M                                                                     
Set clk81 to 24M                                                                       
A53 clk: 1200 MHz                                                                      
A73 clk: 1200 MHz                                                                      
CLK81: 166.6M                                                                          
smccc: 00050a80                                                                        
DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01                
board id: 8                                                                            
Load FIP HDR from SD, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0      
fw parse done                                                                          
Load ddrfw from SD, src: 0x00060200, des: 0xfffd0000, size: 0x0000c000, part: 0        
Load ddrfw from SD, src: 0x00038200, des: 0xfffd0000, size: 0x00004000, part: 0        
PIEI prepare done                                                                      
fastboot data load                                                                     
fastboot data verify                                                                   
verify result: 266                                                                     
Cfg max: 4, cur: 1. Board id: 255. Force loop cfg                                      
LPDDR4 probe                                                                           
ddr clk to 1608MHz                                                                     
Load ddrfw from SD, src: 0x0003c200, des: 0xfffd0000, size: 0x0000c000, part: 0        
                                                                                       
dmc_version 0001                                                                       
Check phy result                                                                       
INFO : End of CA training                                                              
INFO : End of initialization                                                           
INFO : Training has run successfully!                                                  
Check phy result                                                                       
INFO : End of initialization                                                           
INFO : End of read enable training                                                     
INFO : End of fine write leveling                                                      
INFO : End of Write leveling coarse delay                                              
INFO : Training has run successfully!                                                  
Check phy result                                                                       
INFO : End of initialization                                                           
INFO : End of read dq deskew training                                                  
INFO : End of MPR read delay center optimization                                       
INFO : End of write delay center optimization                                          
INFO : End of read delay center optimization                                           
INFO : End of max read latency training                                                
INFO : Training has run successfully!                                                  
1D training succeed                                                                    
Load ddrfw from SD, src: 0x00048200, des: 0xfffd0000, size: 0x0000c000, part: 0        
Check phy result                                                                       
INFO : End of initialization                                                           
INFO : End of 2D read delay Voltage center optimization                                
INFO : End of 2D read delay Voltage center optimization                                
INFO : End of 2D write delay Voltage center optimization                               
INFO : End of 2D write delay Voltage center optimization                               
INFO : Training has run successfully!                                                  
                                                                                       
channel==0                                                                             
RxClkDly_Margin_A0==87 ps 9                                                            
TxDqDly_Margin_A0==106 ps 11                                                           
RxClkDly_Margin_A1==77 ps 8                                                            
TxDqDly_Margin_A1==106 ps 11                                                           
TrainedVREFDQ_A0==26                                                                   
TrainedVREFDQ_A1==27                                                                   
VrefDac_Margin_A0==29                                                                  
DeviceVref_Margin_A0==26                                                               
VrefDac_Margin_A1==30                                                                  
DeviceVref_Margin_A1==27                                                               
                                                                                       
                                                                                       
channel==1                                                                             
RxClkDly_Margin_A0==97 ps 10                                                           
TxDqDly_Margin_A0==106 ps 11                                                           
RxClkDly_Margin_A1==97 ps 10                                                           
TxDqDly_Margin_A1==106 ps 11                                                           
TrainedVREFDQ_A0==26                                                                   
TrainedVREFDQ_A1==26                                                                   
VrefDac_Margin_A0==27                                                                  
DeviceVref_Margin_A0==25                                                               
VrefDac_Margin_A1==27                                                                  
DeviceVref_Margin_A1==25                                                               
                                                                                       
 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004                                 
                                                                                       
soc_vref_reg_value 0x 00000027 00000027 00000026 00000025 00000027 00000025 00000026 03
2D training succeed                                                                    
aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19                
auto size-- 65535DDR cs0 size: 2048MB                                                  
DDR cs1 size: 2048MB                                                                   
DMC_DDR_CTRL: 00e00024DDR size: 3928MB                                                 
cs0 DataBus test pass                                                                  
cs1 DataBus test pass                                                                  
cs0 AddrBus test pass                                                                  
cs1 AddrBus test pass                                                                  
                                                                                       
100bdlr_step_size ps== 450                                                             
result report                                                                          
boot times 0Enable ddr reg access                                                      
Load FIP HDR from SD, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0      
Load BL3X from SD, src: 0x00078200, des: 0x01768000, size: 0x000a0000, part: 0         
0.0;M3 CHK:0;cm4_sp_mode 0                                                             
MVN_1=0x00000000                                                                       
MVN_2=0x00000000                                                                       
[Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]               
OPS=0x10                                                                               
ring efuse init                                                                        
chipver efuse init                                                                     
29 0b 10 00 01 1d 0a 00 00 03 35 38 47 47 52 50                                        
[0.018961 Inits done]                                                                  
secure task start!                                                                     
high task start!                                                                       
low task start!                                                                        
run into bl31                                                                          
NOTICE:  BL31: v1.3(release):4fc40b1                                                   
NOTICE:  BL31: Built : 15:58:17, May 22 2019                                           
NOTICE:  BL31: G12A normal boot!                                                       
NOTICE:  BL31: BL33 decompress pass                                                    
ERROR:   Error initializing runtime service opteed_fast                                
                                                                                       
                                                                                       
U-Boot 2020.04 (Jun 23 2020 - 13:58:11 +0900) khadas-vim3                              
                                                                                       
Model: Khadas VIM3                                                                     
SoC:   Amlogic Meson G12B (A311D) Revision 29:b (10:2)                                 
DRAM:  3.8 GiB                                                                         
MMC:   sd@ffe03000: 0, sd@ffe05000: 1, mmc@ffe07000: 2                                 
Loading Environment from FAT... detect... booted from sd...                            
"uboot.env" not found on mmc-1:1... OK  

It is just stuck here :frowning:

check just now - forks fine

WORKS FINE

additional video

PS: VIM3 ver12 - was tested

PSS: plz check other SD cards - some times is problem

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last mainline uboot images for krescue was fixed

https://dl.khadas.com/Firmware/uboot/mainline/Khadas.UBOOT.mainline.emmc.kresq

sorry its was my fault (was uploaded broken images ) - NOW this problem was FIXED

PS: plz clean old image or just clean/format dump partition

mainline uboot can get some problem with usb SSD

if not enough power - for ssd we can get freezes
problem will be fixed soon

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Yes I trust you that it works fine, but it doesn’t on my device where the emmc is erased completely so there is nothing inside.

I can try the latest krescue image and see if that helps.

Thanks for testing things for me.

Where is the updated krescue image for sd card? There is no update on dl.khadas.com

https://dl.khadas.com/Firmware/Krescue/dump/
https://dl.khadas.com/Firmware/Krescue/images/
https://dl.khadas.com/Firmware/uboot/mainline/

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Thanks for the update.
I will try this now.

Hi @hyphop
Vim1 can boot from sdcard with mainline uboot without the need of TST mode but VIm2 needs TST mode for every boot, Is there any ways to make it boot directly with need of TST mode ?

Any plan to getting to to boot without clean emmc ?

I will be releasing Vim images for our 20.08 images mostly for VIm1, vim2 and vim3, If you can take it and make it into kresq image but only if you do it separate image for each device as we manage separate packages for for each device.

Thanks.

i still don’t understand your problem
and try to clarify again :wink:

  1. normal boot sequence for all amlogic devices VIM1 VIM2 VIM3 VIM3L is emmc -> sd ( spi fplash excluded ), emmc always is first and only if cant boot from emmc device trying bootup from sd
  2. if we are using mainline uboot on emmc / sd - we have next boot sequence spi -> usb -> sd -> emmc - for bootup linux
  3. sure if we have another uboot on emmc - boot sequence not same
  4. sure sd uboot will be ignore if system was booted from emmc uboot
  5. maskrom mode (TST) work fine only for VIM1 VIM2 EDGE

Any plan to getting to to boot without clean emmc ?

read prev messages

I will be releasing Vim images for our 20.08 images mostly for VIm1, vim2 and vim3, If you can take it and make it into kresq image but only if you do it separate image for each device as we manage separate packages for for each device.

yes its easy i will be return to this task very soon and we can make new manjaro images

BTW: i can write some scripts for easy generation krescue images

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