Is it possible to I route I2S input clocks (LRCLK and SCLK) from TDMIN_C to output TDMOUT_B on A311D?
I have an I2S master device which outputs the clocks + data to the SoC at TDMIN_C. I would like the SoC to output the same clocks from TDMOUT_B so that TDMIN_C clocks and TDMOUT_B clocks are in sync. I was hoping that with some register changes I can internally route the clocks from TDMIN_C to TDMOUT_B.
If instead I use MCLK_B to generate LRCLK and SCLK, then TDMOUT_B clocks become out of sync with TDMIN_C clocks.