Finally I’ve been able to setup a serial connection with the board with the goal to understand why it does not boot the OS if I do the installation of UEFI instead of u-boot and I’ve gathered these log messages :
Boot1: 2018-08-06, version: 1.15
CPUId = 0x0
ChipType = 0x10, 218
SdmmcInit=2 0
BootCapSize=100000
UserCapSize=29820MB
FwPartOffset=2000 , 100000
mmc0:cmd5,20
SdmmcInit=0 0
BootCapSize=0
UserCapSize=121942MB
FwPartOffset=2000 , 0
run on sd0
StorageInit ok = 89823
SecureMode = 0
SecureInit read PBA: 0x4
SecureInit read PBA: 0x404
SecureInit read PBA: 0x804
SecureInit read PBA: 0xc04
SecureInit read PBA: 0x1004
SecureInit read PBA: 0x1404
SecureInit read PBA: 0x1804
SecureInit read PBA: 0x1c04
SecureInit ret = 0, SecureMode = 0
GPT 0x3190d20 signature is wrong
LoadTrust Addr:0x4000
No find bl30.bin
No find bl32.bin
Load uboot, ReadLba = 2000
Load OK, addr=0x200000, size=0xf0000
RunBL31 0x10000
NOTICE: BL31: v1.3(debug):51f2096
NOTICE: BL31: Built : 16:24:31, May 6 2019
NOTICE: BL31: Rockchip release version: v1.1
INFO: GICv3 with legacy support detected. ARM GICV3 driver initialized in EL3
INFO: Using opteed sec cpu_context!
INFO: boot cpu mask: 0
INFO: plat_rockchip_pmu_init(1181): pd status 3e
INFO: BL31: Initializing runtime services
WARNING: No OPTEE provided by BL2 boot loader, Booting device without OPTEE initialization. SMC`s dK
ERROR: Error initializing runtime service opteed_fast
INFO: BL31: Preparing for EL3 exit to normal world
INFO: Entry point address = 0x200000
INFO: SPSR = 0x3c9
PLL at FF750000: fbdiv=112, refdiv=2, postdiv1=2, postdiv2=1, vco=1344000 khz, output=672000 khz
Boot PLLs:
APLLL = 400000000
APLLB = 24000000
CPLL = 24000000
DPLL = 800000000
GPLL = 400000000
NPLL = 24000000
VPLL = 24000000
PLL at FF760000: fbdiv=68, refdiv=1, postdiv1=2, postdiv2=1, vco=1632000 khz, output=816000 khz
PLL at FF760020: fbdiv=68, refdiv=1, postdiv1=2, postdiv2=1, vco=1632000 khz, output=816000 khz
PLL at FF760080: fbdiv=100, refdiv=1, postdiv1=3, postdiv2=1, vco=2400000 khz, output=800000 khz
PLL at FF7600A0: fbdiv=125, refdiv=1, postdiv1=3, postdiv2=1, vco=3000000 khz, output=1000000 khz
PLL at FF760060: fbdiv=100, refdiv=1, postdiv1=3, postdiv2=1, vco=2400000 khz, output=800000 khz
After clock init:
APLLL = 816000000
APLLB = 816000000
CPLL = 800000000
DPLL = 800000000
GPLL = 800000000
NPLL = 1000000000
VPLL = 24000000
PLL at FF760000: fbdiv=54, refdiv=1, postdiv1=1, postdiv2=1, vco=1296000 khz, output=1296000 khz
PLL at FF760020: fbdiv=70, refdiv=1, postdiv1=1, postdiv2=1, vco=1680000 khz, output=1680000 khz
�������� : FROZEN : No more messages.
it’s not clear why it hangs. Someone has a vague idea ?