How to force SD card boot mode on vim3?

Which Khadas SBC do you use?

vim3

Which system do you use? Android, Ubuntu, OOWOW or others?

Android

Which version of system do you use? Khadas official images, self built images, or others?

official images

Please describe your issue below:

While writing new image to eMMC from krescue running sd card, the image was written partitally only due to power cut in between, now board boots from eMMC and before it reaches u-boot console it gets reset, how can I force sd boot on vim3 pro board so that I can recover the board?

Post a console log of your issue below:

bl2_stage_init 0x01
bl2_stage_init 0x81
hw id: 0x0000 - pwm id 0x01
bl2_stage_init 0xc1
bl2_stage_init 0x02

L0:00000000
L1:20000703
L2:00008067
L3:14000000
B2:00402000
B1:e0f83180

TE: 179578

BL2 Built : 19:23:21, Sep 18 2020. g12b g9fde858 - gongwei.chen@droid11-sz

Board ID = 8
Set A53 clk to 24M
Set A73 clk to 24M
Set clk81 to 24M
A53 clk: 1200 MHz
A73 clk: 1200 MHz
CLK81: 166.6M
smccc: 0003065d
eMMC boot @ 0
sw8 s
board id: 8
Load FIP HDR DDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0
Get wrong ddr fw magic! Error!!
fw parse done
PIEI prepare done
00000000
emmc switch 1 ok
00000000
emmc switch 2 ok
 NO find ddr boot_info from eMMC
fastboot data verify
result: 255
Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
LPDDR4 probe

LPDDR4_PHY_V_0_1_22-Built : 14:57:26, Sep  1 2020. g12b g3c95fed - gongwei.chen@droid11-sz
ddr clk to 1608MHz
00000000
emmc switch 0 ok

dmc_version 0001
Check phy result
INFO : End of CA training
INFO : End of initialization
INFO : Training has run successfully!
Check phy result
INFO : End of initialization
INFO : End of read enable training
INFO : End of fine write leveling
INFO : End of read dq deskew training
INFO : End of MPR read delay center optimization
INFO : End of Write leveling coarse delay
INFO : End of read delay center optimization
INFO : Training has run successfully!
Check phy result
INFO : End of initialization
INFO : End of MPR read delay center optimization
INFO : End of write delay center optimization
INFO : End of read delay center optimization
INFO : End of max read latency training
INFO : Training has run successfully!
1D training succeed
Check phy result
INFO : End of initialization
INFO : End of 2D read delay Voltage center optimization
INFO : End of 2D read delay Voltage center optimization
INFO : End of 2D write delay Voltage center optimization
INFO : End of 2D write delay Voltage center optimization
INFO : Training has run successfully!

soc_vref_reg_value 0x 0000002a 0000002a 00000029 00000028 00000029 00000029 0000002a 0000002a 00000028 00000026 00000029 00000028 0000002a 00000028 00000025 00000028 00000029 00000029 00000029 00000026 00000027 00000027 00000027 00000027 00000029 00000028 00000029 0000002a 0000002a 00000028 00000028 0000002b dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004 
 dram_vref_reg_value 0x 00000013
2D training succeed
auto size-- 65535DDR cs0 size: 2048MB
DDR cs1 size: 2048MB
DMC_DDR_CTRL: 00e00024DDR size: 3928MB
cs0 DataBus test pass
cs1 DataBus test pass
cs0 AddrBus test pass
cs1 AddrBus test pass

non-sec scramble use zero key
ddr scramble enabled

100bdlr_step_size ps== 425
result report
boot times 0Enable ddr reg access
00000000
emmc switch 3 ok
Authentication key not yet programmed
get rpmb counter error 0x00000007
00000000
emmc switch 0 ok
Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
Load BL3X from eMMC, src: 0x00078200, des: 0x01768000, size: 0x0010ac00, part: 0
BL33 CHK: 0x000000ff ADDR 017a5970
Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 1
00000000
emmc switch 1 ok
FIP HDR CHK: 0x000000ff ADDR 0x01700000
Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 2
00000000
emmc switch 2 ok
FIP HDR CHK: 0x000000ff ADDR 0x01700000
reset...

Hello @jvgediya

In this situation, you may need to relash the image.

https://docs.khadas.com/products/sbc/vim3/install-os/install-os-into-emmc-via-usb-tool